--- trunk/src/cpus/README_DYNTRANS	2007/10/08 16:21:06	33
+++ trunk/src/cpus/README_DYNTRANS	2007/10/08 16:21:17	34
@@ -1,4 +1,9 @@
-$Id: README_DYNTRANS,v 1.12 2006/10/13 05:01:19 debug Exp $
+$Id: README_DYNTRANS,v 1.13 2007/02/11 10:47:30 debug Exp $
+
+This README is old. Hm.
+
+
+---------------------
 
 Dyntrans TODO:
 
@@ -31,45 +36,3 @@
 	(*) Delay slot in SHcompact?
 
 
-  x)  instr_call sequence analysis support? (For handtuning combinations.)
-
-  x)  opcode statistics support?
-		TODO: is instr_call statistics enough?
-
-  x)  load/stores:
-		o)  perhaps refactor/reuse common load/store code?
-		o)  support for archs that allow transparent
-		    unaligned load/stores (ppc, x86 etc)
-		o)  alignment checks ==> exceptions
-		o)  native byte order ==> faster loads, etc.
-
-  x)  actual cache emulation
-
-  x)  SMP: detect when an instruction such as ll/sc or cas is used,
-	    and "synchronize" approximately the number of executed instructions
-	    (or cycles) across all CPUs.
-      Problem: devices such as dev_mp don't work well with such a synch.
-		scheme.
-
-  x)  support for variable-length instructions (x86, m68k, i960, ...)
-		Current solution: ic->arg[0] contains the length of the
-				instruction (in bytes), and next_ic is
-				automatically updated.
-		Problem: what about instructions crossing a (virtual)
-			page boundary? They cannot be translated once
-			and for all :( and must be interpreted slowly!
-
-  x)  support for THUMB, MIPS16, userland SH  (arm, mips, sh)
-
-  x)  support for Delay slots!  (mips, sparc, hppa, SHcompact?)
-
-  x)  various register-window archs (SPARC etc)
-
-  x)  Alpha: hahaha, zapnot and inserts/extracts don't
-	    compile into very nice code :-|  fix this
-		Solution: if short assembly language snippets can be
-		compiled on the current host, then compile such snippets
-		for alpha_instr_zapnot etc.
-
-  x)  pc532? 6502? 6800? etc
-