/[gxemul]/trunk/src/cpus/README_DYNTRANS
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 29 by dpavlin, Mon Oct 8 16:19:56 2007 UTC revision 30 by dpavlin, Mon Oct 8 16:20:40 2007 UTC
# Line 1  Line 1 
1  $Id: README_DYNTRANS,v 1.9 2006/03/15 20:34:05 debug Exp $  $Id: README_DYNTRANS,v 1.11 2006/07/27 02:18:07 debug Exp $
   
 -------------------------------------------------------------------  
   
 PPC optimizations TODO:  
   
         find high-level bottlenecks!  
   
         inline cr0 field calculation  
   
         load/store with r1 as base?  
   
         multiple load/stores in a row (especially with base = r1)  
   
         almost all branches are of the "general" form now, they don't  
                 need to be.  
   
         combinations of compare + branch, similar to arm?  
   
 -------------------------------------------------------------------  
   
   
2    
3  Dyntrans TODO:  Dyntrans TODO:
4    
# Line 37  Dyntrans TODO: Line 16  Dyntrans TODO:
16          i960            32-bit + variable               32              ?          i960            32-bit + variable               32              ?
17          IA64            128-bit                         64              no          IA64            128-bit                         64              no
18          M68K            16-bit + variable               32              no          M68K            16-bit + variable               32              no
19          M88K            ?                               32 (?)          ?          M88K            32-bit (+var?)                  32              ?
20          MIPS            32-bit, 16-bit (MIPS16)         64/32           yes          MIPS            32-bit, 16-bit (MIPS16)         64/32           yes
21          OpenRISC        ?                               ?               ?          OpenRISC        ?                               ?               ?
22          PC532           ?                               32 (?)          ?          PC532           ?                               32 (?)          ?
23          POWER/PPC       32-bit                          64/32           no          POWER/PPC       32-bit                          64/32           no
24          SH              32-bit, 16-bit (SHcompact)      64/32           yes(*)          SH              32-bit, 16-bit (SHcompact)      64/32           yes(*)
25          SPARC           32-bit                          64/32           yes          SPARC           32-bit                          64/32           yes
26            Transputer      8-bit                           32/16           no
27          x86             8-bit + variable                64/32/16        no          x86             8-bit + variable                64/32/16        no
28          VAX             8-bit + variable                32              no          VAX             8-bit + variable                32              no
29    
30          (*) Delay slot in SHcompact?          (*) Delay slot in SHcompact?
31    
32    
   x)  call/return address cache?  
   
33    x)  instr_call sequence analysis support? (For handtuning combinations.)    x)  instr_call sequence analysis support? (For handtuning combinations.)
34    
35    x)  opcode statistics support?    x)  opcode statistics support?
# Line 69  Dyntrans TODO: Line 47  Dyntrans TODO:
47    x)  SMP: detect when an instruction such as ll/sc or cas is used,    x)  SMP: detect when an instruction such as ll/sc or cas is used,
48              and "synchronize" approximately the number of executed instructions              and "synchronize" approximately the number of executed instructions
49              (or cycles) across all CPUs.              (or cycles) across all CPUs.
50          Problem: devices such as dev_mp don't work well with such a synch.
51                    scheme.
52    
53    x)  support for variable-length instructions (x86, m68k, i960, ...)    x)  support for variable-length instructions (x86, m68k, i960, ...)
54                  Solution:  don't increase the next_ic between every                  Current solution: ic->arg[0] contains the length of the
55                          instruction, but let each instruction's handler do                                  instruction (in bytes), and next_ic is
56                          that for itself.                                  automatically updated.
57                  Problem: what about instructions crossing a (virtual)                  Problem: what about instructions crossing a (virtual)
58                          page boundary? They cannot be translated once                          page boundary? They cannot be translated once
59                          and for all :( and must be interpreted slowly!                          and for all :( and must be interpreted slowly!
# Line 90  Dyntrans TODO: Line 70  Dyntrans TODO:
70                  compiled on the current host, then compile such snippets                  compiled on the current host, then compile such snippets
71                  for alpha_instr_zapnot etc.                  for alpha_instr_zapnot etc.
72    
73    x)  x86: convert to dyntrans. LOTS of stuff to consider.    x)  pc532? 6502? 6800? etc
   
   x)  88k? vax? pc532? 6502? 6800? etc  
74    

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