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$Id: README_DYNTRANS,v 1.9 2006/03/15 20:34:05 debug Exp $ |
$Id: README_DYNTRANS,v 1.11 2006/07/27 02:18:07 debug Exp $ |
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PPC optimizations TODO: |
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find high-level bottlenecks! |
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inline cr0 field calculation |
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load/store with r1 as base? |
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multiple load/stores in a row (especially with base = r1) |
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almost all branches are of the "general" form now, they don't |
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need to be. |
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combinations of compare + branch, similar to arm? |
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Dyntrans TODO: |
Dyntrans TODO: |
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i960 32-bit + variable 32 ? |
i960 32-bit + variable 32 ? |
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IA64 128-bit 64 no |
IA64 128-bit 64 no |
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M68K 16-bit + variable 32 no |
M68K 16-bit + variable 32 no |
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M88K ? 32 (?) ? |
M88K 32-bit (+var?) 32 ? |
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MIPS 32-bit, 16-bit (MIPS16) 64/32 yes |
MIPS 32-bit, 16-bit (MIPS16) 64/32 yes |
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OpenRISC ? ? ? |
OpenRISC ? ? ? |
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PC532 ? 32 (?) ? |
PC532 ? 32 (?) ? |
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POWER/PPC 32-bit 64/32 no |
POWER/PPC 32-bit 64/32 no |
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SH 32-bit, 16-bit (SHcompact) 64/32 yes(*) |
SH 32-bit, 16-bit (SHcompact) 64/32 yes(*) |
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SPARC 32-bit 64/32 yes |
SPARC 32-bit 64/32 yes |
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Transputer 8-bit 32/16 no |
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x86 8-bit + variable 64/32/16 no |
x86 8-bit + variable 64/32/16 no |
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VAX 8-bit + variable 32 no |
VAX 8-bit + variable 32 no |
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(*) Delay slot in SHcompact? |
(*) Delay slot in SHcompact? |
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x) call/return address cache? |
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x) instr_call sequence analysis support? (For handtuning combinations.) |
x) instr_call sequence analysis support? (For handtuning combinations.) |
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x) opcode statistics support? |
x) opcode statistics support? |
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x) SMP: detect when an instruction such as ll/sc or cas is used, |
x) SMP: detect when an instruction such as ll/sc or cas is used, |
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and "synchronize" approximately the number of executed instructions |
and "synchronize" approximately the number of executed instructions |
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(or cycles) across all CPUs. |
(or cycles) across all CPUs. |
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Problem: devices such as dev_mp don't work well with such a synch. |
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scheme. |
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x) support for variable-length instructions (x86, m68k, i960, ...) |
x) support for variable-length instructions (x86, m68k, i960, ...) |
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Solution: don't increase the next_ic between every |
Current solution: ic->arg[0] contains the length of the |
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instruction, but let each instruction's handler do |
instruction (in bytes), and next_ic is |
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that for itself. |
automatically updated. |
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Problem: what about instructions crossing a (virtual) |
Problem: what about instructions crossing a (virtual) |
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page boundary? They cannot be translated once |
page boundary? They cannot be translated once |
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and for all :( and must be interpreted slowly! |
and for all :( and must be interpreted slowly! |
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compiled on the current host, then compile such snippets |
compiled on the current host, then compile such snippets |
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for alpha_instr_zapnot etc. |
for alpha_instr_zapnot etc. |
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x) x86: convert to dyntrans. LOTS of stuff to consider. |
x) pc532? 6502? 6800? etc |
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x) 88k? vax? pc532? 6502? 6800? etc |
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