Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $ 20060723 More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp, eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move, wcnt, add, bcnt). Adding more SPARC instructions (andcc, addcc, bl, rdpr). Progress on the igsfb framebuffer used by NetBSD/netwinder. Enabling 8-bit fills in dev_fb. NetBSD/netwinder 3.0.1 can now run from a disk image :-) 20060724 Cleanup/performance fix for 64-bit virtual translation table updates (by removing the "timestamp" stuff). A full NetBSD/pmax 3.0.1 install for R4400 has dropped from 667 seconds to 584 :) Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit). Adding some MIPS instruction combinations (3*lw, and 3*addu). The 8048 keyboard now turns off interrupt enable between the KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6. Not causing PPC DEC interrupts if PPC_NO_DEC is set for a specific CPU; NetBSD/bebox gets slightly further than before. Adding some more SPARC instructions: branches, udiv. 20060725 Refreshing dev_pckbc.c a little. Cleanups for the SH emulation mode, and adding the first "compact" (16-bit) instructions: various simple movs, nop, shll, stc, or, ldc. 20060726 Adding dummy "pcn" (AMD PCnet NIC) PCI glue. 20060727 Various cleanups; removing stuff from cpu.h, such as running_translated (not really meaningful anymore), and page flags (breaking into the debugger clears all translations anyway). Minor MIPS instruction combination updates. 20060807 Expanding the 3*sw and 3*lw MIPS instruction combinations to work with 2* and 4* too, resulting in a minor performance gain. Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait" instruction (when emulating 1 cpu). 20060808 Experimenting with some more MIPS instruction combinations. Implementing support for showing a (hardcoded 12x22) text cursor in igsfb. 20060809 Simplifying the NetBSD/evbmips (Malta) install instructions somewhat (by using a NetBSD/pmax ramdisk install kernel). 20060812 Experimenting more with the MIPS 'wait' instruction. PCI configuration register writes can now be handled, which allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.) 20060813 Updating dev_gt.c based on numbers from Alec Voropay, to enable Linux 2.6 to use PCI on Malta. Continuing on Algor interrupt stuff. 20060814 Adding support for routing ISA interrupts to two different interrupts, making it possible to run NetBSD/algor :-) 20060814-15 Testing for the release. ============== RELEASE 0.4.2 ==============
1 | dpavlin | 30 | $Id: README_DYNTRANS,v 1.11 2006/07/27 02:18:07 debug Exp $ |
2 | dpavlin | 14 | |
3 | Dyntrans TODO: | ||
4 | |||
5 | x) Make sure that all of these could work, at least in theory: | ||
6 | |||
7 | Instruction Word Delay | ||
8 | Arch.: length: size: slot: | ||
9 | ------ ------- ----- ----- | ||
10 | Alpha 32-bit 64 no | ||
11 | ARM 32-bit, 16-bit (Thumb) 32 no | ||
12 | dpavlin | 24 | Atmel AVR 16-bit + variable 8 no |
13 | dpavlin | 20 | F-CPU ? ? ? |
14 | dpavlin | 24 | H8 16-bit 8/16 no |
15 | dpavlin | 14 | HPPA 32-bit 64/32 yes |
16 | i960 32-bit + variable 32 ? | ||
17 | IA64 128-bit 64 no | ||
18 | M68K 16-bit + variable 32 no | ||
19 | dpavlin | 30 | M88K 32-bit (+var?) 32 ? |
20 | dpavlin | 14 | MIPS 32-bit, 16-bit (MIPS16) 64/32 yes |
21 | dpavlin | 20 | OpenRISC ? ? ? |
22 | dpavlin | 14 | PC532 ? 32 (?) ? |
23 | POWER/PPC 32-bit 64/32 no | ||
24 | SH 32-bit, 16-bit (SHcompact) 64/32 yes(*) | ||
25 | SPARC 32-bit 64/32 yes | ||
26 | dpavlin | 30 | Transputer 8-bit 32/16 no |
27 | dpavlin | 14 | x86 8-bit + variable 64/32/16 no |
28 | VAX 8-bit + variable 32 no | ||
29 | |||
30 | (*) Delay slot in SHcompact? | ||
31 | |||
32 | |||
33 | x) instr_call sequence analysis support? (For handtuning combinations.) | ||
34 | |||
35 | x) opcode statistics support? | ||
36 | TODO: is instr_call statistics enough? | ||
37 | |||
38 | x) load/stores: | ||
39 | dpavlin | 22 | o) perhaps refactor/reuse common load/store code? |
40 | dpavlin | 14 | o) support for archs that allow transparent |
41 | unaligned load/stores (ppc, x86 etc) | ||
42 | o) alignment checks ==> exceptions | ||
43 | o) native byte order ==> faster loads, etc. | ||
44 | |||
45 | x) actual cache emulation | ||
46 | |||
47 | x) SMP: detect when an instruction such as ll/sc or cas is used, | ||
48 | and "synchronize" approximately the number of executed instructions | ||
49 | (or cycles) across all CPUs. | ||
50 | dpavlin | 30 | Problem: devices such as dev_mp don't work well with such a synch. |
51 | scheme. | ||
52 | dpavlin | 14 | |
53 | x) support for variable-length instructions (x86, m68k, i960, ...) | ||
54 | dpavlin | 30 | Current solution: ic->arg[0] contains the length of the |
55 | instruction (in bytes), and next_ic is | ||
56 | automatically updated. | ||
57 | dpavlin | 14 | Problem: what about instructions crossing a (virtual) |
58 | page boundary? They cannot be translated once | ||
59 | and for all :( and must be interpreted slowly! | ||
60 | |||
61 | x) support for THUMB, MIPS16, userland SH (arm, mips, sh) | ||
62 | |||
63 | x) support for Delay slots! (mips, sparc, hppa, SHcompact?) | ||
64 | |||
65 | x) various register-window archs (SPARC etc) | ||
66 | |||
67 | x) Alpha: hahaha, zapnot and inserts/extracts don't | ||
68 | compile into very nice code :-| fix this | ||
69 | Solution: if short assembly language snippets can be | ||
70 | compiled on the current host, then compile such snippets | ||
71 | for alpha_instr_zapnot etc. | ||
72 | |||
73 | dpavlin | 30 | x) pc532? 6502? 6800? etc |
74 | dpavlin | 14 |
ViewVC Help | |
Powered by ViewVC 1.1.26 |