/[gxemul]/trunk/src/cpus/Makefile.skel
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Contents of /trunk/src/cpus/Makefile.skel

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (11 years, 11 months ago) by dpavlin
File size: 8005 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 #
2 # $Id: Makefile.skel,v 1.27 2006/10/25 09:24:06 debug Exp $
3 #
4 # Makefile for GXemul src/cpus
5 #
6
7 CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
8
9 OBJS=$(CPU_ARCHS) $(CPU_BACKENDS)
10 TOOLS=generate_head generate_tail $(CPU_TOOLS)
11
12
13 all: $(TOOLS)
14 $(MAKE) buildobjs
15
16
17 buildobjs: $(OBJS)
18
19
20 $(OBJS): Makefile
21
22
23
24 ###############################################################################
25
26 cpu_alpha.o: cpu_alpha.c cpu_alpha_instr.c cpu_dyntrans.c ../memory_rw.c \
27 tmp_alpha_head.c tmp_alpha_tail.c
28
29 cpu_alpha_instr.c: cpu_alpha_instr_alu.c tmp_alpha_misc.c
30
31 tmp_alpha_misc.c: cpu_alpha_instr_loadstore.c generate_alpha_misc
32 ./generate_alpha_misc > tmp_alpha_misc.c
33
34 tmp_alpha_head.c: generate_head
35 ./generate_head alpha Alpha > tmp_alpha_head.c
36
37 tmp_alpha_tail.c: generate_tail
38 ./generate_tail alpha Alpha > tmp_alpha_tail.c
39
40
41 ###############################################################################
42
43 cpu_arm.o: cpu_arm.c cpu_arm_instr.c cpu_dyntrans.c ../memory_rw.c \
44 tmp_arm_head.c tmp_arm_tail.c
45
46 cpu_arm_instr.c: cpu_arm_instr_misc.c
47
48 tmp_arm_loadstore.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
49 ./generate_arm_loadstore > tmp_arm_loadstore.c
50
51 tmp_arm_multi.c: generate_arm_multi cpu_arm_multi.txt
52 ./generate_arm_multi `cat cpu_arm_multi.txt` > tmp_arm_multi.c
53
54 tmp_arm_dpi.c: cpu_arm_instr_dpi.c generate_arm_dpi
55 ./generate_arm_dpi > tmp_arm_dpi.c
56
57 tmp_arm_r0.c: generate_arm_r
58 ./generate_arm_r 0x000 0x0ff > tmp_arm_r0.c
59 tmp_arm_r1.c: generate_arm_r
60 ./generate_arm_r 0x100 0x1ff > tmp_arm_r1.c
61 tmp_arm_r2.c: generate_arm_r
62 ./generate_arm_r 0x200 0x2ff > tmp_arm_r2.c
63 tmp_arm_r3.c: generate_arm_r
64 ./generate_arm_r 0x300 0x3ff > tmp_arm_r3.c
65 tmp_arm_r4.c: generate_arm_r
66 ./generate_arm_r 0x400 0x4ff > tmp_arm_r4.c
67 tmp_arm_r5.c: generate_arm_r
68 ./generate_arm_r 0x500 0x5ff > tmp_arm_r5.c
69 tmp_arm_r6.c: generate_arm_r
70 ./generate_arm_r 0x600 0x6ff > tmp_arm_r6.c
71 tmp_arm_r7.c: generate_arm_r
72 ./generate_arm_r 0x700 0x7ff > tmp_arm_r7.c
73 tmp_arm_r8.c: generate_arm_r
74 ./generate_arm_r 0x800 0x8ff > tmp_arm_r8.c
75 tmp_arm_r9.c: generate_arm_r
76 ./generate_arm_r 0x900 0x9ff > tmp_arm_r9.c
77 tmp_arm_ra.c: generate_arm_r
78 ./generate_arm_r 0xa00 0xaff > tmp_arm_ra.c
79 tmp_arm_rb.c: generate_arm_r
80 ./generate_arm_r 0xb00 0xbff > tmp_arm_rb.c
81 tmp_arm_rc.c: generate_arm_r
82 ./generate_arm_r 0xc00 0xcff > tmp_arm_rc.c
83 tmp_arm_rd.c: generate_arm_r
84 ./generate_arm_r 0xd00 0xdff > tmp_arm_rd.c
85 tmp_arm_re.c: generate_arm_r
86 ./generate_arm_r 0xe00 0xeff > tmp_arm_re.c
87 tmp_arm_rf.c: generate_arm_r
88 ./generate_arm_r 0xf00 0xfff > tmp_arm_rf.c
89
90 tmp_arm_r.c: generate_arm_r
91 ./generate_arm_r 0 0 > tmp_arm_r.c
92
93 tmp_arm_head.c: generate_head
94 ./generate_head arm ARM > tmp_arm_head.c
95
96 tmp_arm_tail.c: generate_tail
97 ./generate_tail arm ARM > tmp_arm_tail.c
98
99
100 ###############################################################################
101
102 cpu_avr.o: cpu_avr.c cpu_avr_instr.c cpu_dyntrans.c ../memory_rw.c \
103 tmp_avr_head.c tmp_avr_tail.c
104
105 tmp_avr_head.c: generate_head
106 ./generate_head avr AVR > tmp_avr_head.c
107
108 tmp_avr_tail.c: generate_tail
109 ./generate_tail avr AVR > tmp_avr_tail.c
110
111
112 ###############################################################################
113
114 cpu_avr32.o: cpu_avr32.c cpu_avr32_instr.c cpu_dyntrans.c ../memory_rw.c \
115 tmp_avr32_head.c tmp_avr32_tail.c
116
117 tmp_avr32_head.c: generate_head
118 ./generate_head avr32 AVR32 > tmp_avr32_head.c
119
120 tmp_avr32_tail.c: generate_tail
121 ./generate_tail avr32 AVR32 > tmp_avr32_tail.c
122
123
124 ###############################################################################
125
126 cpu_rca180x.o: cpu_rca180x.c cpu_rca180x_instr.c cpu_dyntrans.c ../memory_rw.c \
127 tmp_rca180x_head.c tmp_rca180x_tail.c
128
129 tmp_rca180x_head.c: generate_head
130 ./generate_head rca180x RCA180X > tmp_rca180x_head.c
131
132 tmp_rca180x_tail.c: generate_tail
133 ./generate_tail rca180x RCA180X > tmp_rca180x_tail.c
134
135
136 ###############################################################################
137
138 cpu_hppa.o: cpu_hppa.c cpu_hppa_instr.c cpu_dyntrans.c ../memory_rw.c \
139 tmp_hppa_head.c tmp_hppa_tail.c
140
141 tmp_hppa_head.c: generate_head
142 ./generate_head hppa HPPA > tmp_hppa_head.c
143
144 tmp_hppa_tail.c: generate_tail
145 ./generate_tail hppa HPPA > tmp_hppa_tail.c
146
147
148 ###############################################################################
149
150 cpu_i960.o: cpu_i960.c cpu_i960_instr.c cpu_dyntrans.c ../memory_rw.c \
151 tmp_i960_head.c tmp_i960_tail.c
152
153 tmp_i960_head.c: generate_head
154 ./generate_head i960 i960 > tmp_i960_head.c
155
156 tmp_i960_tail.c: generate_tail
157 ./generate_tail i960 i960 > tmp_i960_tail.c
158
159
160 ###############################################################################
161
162 cpu_ia64.o: cpu_ia64.c cpu_ia64_instr.c cpu_dyntrans.c ../memory_rw.c \
163 tmp_ia64_head.c tmp_ia64_tail.c
164
165 tmp_ia64_head.c: generate_head
166 ./generate_head ia64 IA64 > tmp_ia64_head.c
167
168 tmp_ia64_tail.c: generate_tail
169 ./generate_tail ia64 IA64 > tmp_ia64_tail.c
170
171
172 ###############################################################################
173
174 cpu_m68k.o: cpu_m68k.c cpu_m68k_instr.c cpu_dyntrans.c ../memory_rw.c \
175 tmp_m68k_head.c tmp_m68k_tail.c
176
177 tmp_m68k_head.c: generate_head
178 ./generate_head m68k M68K > tmp_m68k_head.c
179
180 tmp_m68k_tail.c: generate_tail
181 ./generate_tail m68k M68K > tmp_m68k_tail.c
182
183
184 ###############################################################################
185
186 cpu_mips.o: cpu_mips.c cpu_dyntrans.c memory_mips.c \
187 cpu_mips_instr.c tmp_mips_loadstore.c tmp_mips_head.c tmp_mips_tail.c
188
189 memory_mips.c: ../memory_rw.c memory_mips_v2p.c
190
191 tmp_mips_loadstore.c: cpu_mips_instr_loadstore.c generate_mips_loadstore
192 ./generate_mips_loadstore > tmp_mips_loadstore.c
193
194 tmp_mips_head.c: generate_head
195 ./generate_head mips MIPS > tmp_mips_head.c
196
197 tmp_mips_tail.c: generate_tail
198 ./generate_tail mips MIPS > tmp_mips_tail.c
199
200
201 ###############################################################################
202
203 cpu_ppc.o: cpu_ppc.c cpu_ppc_instr.c cpu_dyntrans.c memory_ppc.c \
204 ../memory_rw.c tmp_ppc_head.c tmp_ppc_tail.c tmp_ppc_loadstore.c
205
206 tmp_ppc_loadstore.c: cpu_ppc_instr_loadstore.c generate_ppc_loadstore
207 ./generate_ppc_loadstore > tmp_ppc_loadstore.c
208
209 tmp_ppc_head.c: generate_head
210 ./generate_head ppc PPC > tmp_ppc_head.c
211
212 tmp_ppc_tail.c: generate_tail
213 ./generate_tail ppc PPC > tmp_ppc_tail.c
214
215
216 ###############################################################################
217
218 cpu_sh.o: cpu_sh.c cpu_sh_instr.c cpu_dyntrans.c ../memory_rw.c \
219 tmp_sh_head.c tmp_sh_tail.c
220
221 tmp_sh_head.c: generate_head
222 ./generate_head sh SH > tmp_sh_head.c
223
224 tmp_sh_tail.c: generate_tail
225 ./generate_tail sh SH > tmp_sh_tail.c
226
227
228 ###############################################################################
229
230 cpu_sparc.o: cpu_sparc.c cpu_sparc_instr.c cpu_dyntrans.c ../memory_rw.c \
231 tmp_sparc_head.c tmp_sparc_tail.c tmp_sparc_loadstore.c
232
233 tmp_sparc_loadstore.c: cpu_sparc_instr_loadstore.c generate_sparc_loadstore
234 ./generate_sparc_loadstore > tmp_sparc_loadstore.c
235
236 tmp_sparc_head.c: generate_head
237 ./generate_head sparc SPARC > tmp_sparc_head.c
238
239 tmp_sparc_tail.c: generate_tail
240 ./generate_tail sparc SPARC > tmp_sparc_tail.c
241
242
243 ###############################################################################
244
245 cpu_transputer.o: cpu_transputer.c cpu_transputer_instr.c cpu_dyntrans.c \
246 ../memory_rw.c tmp_transputer_head.c tmp_transputer_tail.c
247
248 tmp_transputer_head.c: generate_head
249 ./generate_head transputer Transputer > tmp_transputer_head.c
250
251 tmp_transputer_tail.c: generate_tail
252 ./generate_tail transputer Transputer > tmp_transputer_tail.c
253
254
255 ###############################################################################
256
257 cpu_x86.o: cpu_x86.c cpu_x86_instr.c cpu_dyntrans.c ../memory_rw.c \
258 memory_x86.c tmp_x86_head.c tmp_x86_tail.c
259
260 tmp_x86_head.c: generate_head
261 ./generate_head x86 x86 > tmp_x86_head.c
262
263 tmp_x86_tail.c: generate_tail
264 ./generate_tail x86 x86 > tmp_x86_tail.c
265
266
267 ###############################################################################
268
269 clean:
270 rm -f $(OBJS) $(TOOLS) *core tmp_*.c *.gmon experiment_arm_multi
271
272 clean_all: clean
273 rm -f Makefile
274

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