/[gxemul]/trunk/src/cpus/Makefile.skel
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/Makefile.skel

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 1 month ago) by dpavlin
File size: 7269 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 #
2 # $Id: Makefile.skel,v 1.24 2006/07/20 21:52:59 debug Exp $
3 #
4 # Makefile for GXemul src/cpus
5 #
6
7 CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
8
9 OBJS=$(CPU_ARCHS) $(CPU_BACKENDS)
10 TOOLS=generate_head generate_tail $(CPU_TOOLS)
11
12
13 all: $(TOOLS)
14 $(MAKE) buildobjs
15
16
17 buildobjs: $(OBJS)
18
19
20 $(OBJS): Makefile
21
22
23
24 ###############################################################################
25
26 cpu_alpha.o: cpu_alpha.c cpu_alpha_instr.c cpu_dyntrans.c ../memory_rw.c \
27 tmp_alpha_head.c tmp_alpha_tail.c
28
29 cpu_alpha_instr.c: cpu_alpha_instr_alu.c tmp_alpha_misc.c
30
31 tmp_alpha_misc.c: cpu_alpha_instr_loadstore.c generate_alpha_misc
32 ./generate_alpha_misc > tmp_alpha_misc.c
33
34 tmp_alpha_head.c: generate_head
35 ./generate_head alpha Alpha > tmp_alpha_head.c
36
37 tmp_alpha_tail.c: generate_tail
38 ./generate_tail alpha Alpha > tmp_alpha_tail.c
39
40
41 ###############################################################################
42
43 cpu_arm.o: cpu_arm.c cpu_arm_instr.c cpu_dyntrans.c ../memory_rw.c \
44 tmp_arm_head.c tmp_arm_tail.c
45
46 cpu_arm_instr.c: cpu_arm_instr_misc.c
47
48 tmp_arm_loadstore.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
49 ./generate_arm_loadstore > tmp_arm_loadstore.c
50
51 tmp_arm_multi.c: generate_arm_multi cpu_arm_multi.txt
52 ./generate_arm_multi `cat cpu_arm_multi.txt` > tmp_arm_multi.c
53
54 tmp_arm_dpi.c: cpu_arm_instr_dpi.c generate_arm_dpi
55 ./generate_arm_dpi > tmp_arm_dpi.c
56
57 tmp_arm_r0.c: generate_arm_r
58 ./generate_arm_r 0x000 0x0ff > tmp_arm_r0.c
59 tmp_arm_r1.c: generate_arm_r
60 ./generate_arm_r 0x100 0x1ff > tmp_arm_r1.c
61 tmp_arm_r2.c: generate_arm_r
62 ./generate_arm_r 0x200 0x2ff > tmp_arm_r2.c
63 tmp_arm_r3.c: generate_arm_r
64 ./generate_arm_r 0x300 0x3ff > tmp_arm_r3.c
65 tmp_arm_r4.c: generate_arm_r
66 ./generate_arm_r 0x400 0x4ff > tmp_arm_r4.c
67 tmp_arm_r5.c: generate_arm_r
68 ./generate_arm_r 0x500 0x5ff > tmp_arm_r5.c
69 tmp_arm_r6.c: generate_arm_r
70 ./generate_arm_r 0x600 0x6ff > tmp_arm_r6.c
71 tmp_arm_r7.c: generate_arm_r
72 ./generate_arm_r 0x700 0x7ff > tmp_arm_r7.c
73 tmp_arm_r8.c: generate_arm_r
74 ./generate_arm_r 0x800 0x8ff > tmp_arm_r8.c
75 tmp_arm_r9.c: generate_arm_r
76 ./generate_arm_r 0x900 0x9ff > tmp_arm_r9.c
77 tmp_arm_ra.c: generate_arm_r
78 ./generate_arm_r 0xa00 0xaff > tmp_arm_ra.c
79 tmp_arm_rb.c: generate_arm_r
80 ./generate_arm_r 0xb00 0xbff > tmp_arm_rb.c
81 tmp_arm_rc.c: generate_arm_r
82 ./generate_arm_r 0xc00 0xcff > tmp_arm_rc.c
83 tmp_arm_rd.c: generate_arm_r
84 ./generate_arm_r 0xd00 0xdff > tmp_arm_rd.c
85 tmp_arm_re.c: generate_arm_r
86 ./generate_arm_r 0xe00 0xeff > tmp_arm_re.c
87 tmp_arm_rf.c: generate_arm_r
88 ./generate_arm_r 0xf00 0xfff > tmp_arm_rf.c
89
90 tmp_arm_r.c: generate_arm_r
91 ./generate_arm_r 0 0 > tmp_arm_r.c
92
93 tmp_arm_head.c: generate_head
94 ./generate_head arm ARM > tmp_arm_head.c
95
96 tmp_arm_tail.c: generate_tail
97 ./generate_tail arm ARM > tmp_arm_tail.c
98
99
100 ###############################################################################
101
102 cpu_avr.o: cpu_avr.c cpu_avr_instr.c cpu_dyntrans.c ../memory_rw.c \
103 tmp_avr_head.c tmp_avr_tail.c
104
105 tmp_avr_head.c: generate_head
106 ./generate_head avr AVR > tmp_avr_head.c
107
108 tmp_avr_tail.c: generate_tail
109 ./generate_tail avr AVR > tmp_avr_tail.c
110
111
112 ###############################################################################
113
114 cpu_hppa.o: cpu_hppa.c cpu_hppa_instr.c cpu_dyntrans.c ../memory_rw.c \
115 tmp_hppa_head.c tmp_hppa_tail.c
116
117 tmp_hppa_head.c: generate_head
118 ./generate_head hppa HPPA > tmp_hppa_head.c
119
120 tmp_hppa_tail.c: generate_tail
121 ./generate_tail hppa HPPA > tmp_hppa_tail.c
122
123
124 ###############################################################################
125
126 cpu_i960.o: cpu_i960.c cpu_i960_instr.c cpu_dyntrans.c ../memory_rw.c \
127 tmp_i960_head.c tmp_i960_tail.c
128
129 tmp_i960_head.c: generate_head
130 ./generate_head i960 i960 > tmp_i960_head.c
131
132 tmp_i960_tail.c: generate_tail
133 ./generate_tail i960 i960 > tmp_i960_tail.c
134
135
136 ###############################################################################
137
138 cpu_ia64.o: cpu_ia64.c cpu_ia64_instr.c cpu_dyntrans.c ../memory_rw.c \
139 tmp_ia64_head.c tmp_ia64_tail.c
140
141 tmp_ia64_head.c: generate_head
142 ./generate_head ia64 IA64 > tmp_ia64_head.c
143
144 tmp_ia64_tail.c: generate_tail
145 ./generate_tail ia64 IA64 > tmp_ia64_tail.c
146
147
148 ###############################################################################
149
150 cpu_m68k.o: cpu_m68k.c cpu_m68k_instr.c cpu_dyntrans.c ../memory_rw.c \
151 tmp_m68k_head.c tmp_m68k_tail.c
152
153 tmp_m68k_head.c: generate_head
154 ./generate_head m68k M68K > tmp_m68k_head.c
155
156 tmp_m68k_tail.c: generate_tail
157 ./generate_tail m68k M68K > tmp_m68k_tail.c
158
159
160 ###############################################################################
161
162 cpu_mips.o: cpu_mips.c cpu_dyntrans.c memory_mips.c \
163 cpu_mips_instr.c tmp_mips_loadstore.c tmp_mips_head.c tmp_mips_tail.c
164
165 memory_mips.c: ../memory_rw.c memory_mips_v2p.c
166
167 tmp_mips_loadstore.c: cpu_mips_instr_loadstore.c generate_mips_loadstore
168 ./generate_mips_loadstore > tmp_mips_loadstore.c
169
170 tmp_mips_head.c: generate_head
171 ./generate_head mips MIPS > tmp_mips_head.c
172
173 tmp_mips_tail.c: generate_tail
174 ./generate_tail mips MIPS > tmp_mips_tail.c
175
176
177 ###############################################################################
178
179 cpu_ppc.o: cpu_ppc.c cpu_ppc_instr.c cpu_dyntrans.c memory_ppc.c \
180 ../memory_rw.c tmp_ppc_head.c tmp_ppc_tail.c tmp_ppc_loadstore.c
181
182 tmp_ppc_loadstore.c: cpu_ppc_instr_loadstore.c generate_ppc_loadstore
183 ./generate_ppc_loadstore > tmp_ppc_loadstore.c
184
185 tmp_ppc_head.c: generate_head
186 ./generate_head ppc PPC > tmp_ppc_head.c
187
188 tmp_ppc_tail.c: generate_tail
189 ./generate_tail ppc PPC > tmp_ppc_tail.c
190
191
192 ###############################################################################
193
194 cpu_sh.o: cpu_sh.c cpu_sh_instr.c cpu_dyntrans.c ../memory_rw.c \
195 tmp_sh_head.c tmp_sh_tail.c
196
197 tmp_sh_head.c: generate_head
198 ./generate_head sh SH > tmp_sh_head.c
199
200 tmp_sh_tail.c: generate_tail
201 ./generate_tail sh SH > tmp_sh_tail.c
202
203
204 ###############################################################################
205
206 cpu_sparc.o: cpu_sparc.c cpu_sparc_instr.c cpu_dyntrans.c ../memory_rw.c \
207 tmp_sparc_head.c tmp_sparc_tail.c tmp_sparc_loadstore.c
208
209 tmp_sparc_loadstore.c: cpu_sparc_instr_loadstore.c generate_sparc_loadstore
210 ./generate_sparc_loadstore > tmp_sparc_loadstore.c
211
212 tmp_sparc_head.c: generate_head
213 ./generate_head sparc SPARC > tmp_sparc_head.c
214
215 tmp_sparc_tail.c: generate_tail
216 ./generate_tail sparc SPARC > tmp_sparc_tail.c
217
218
219 ###############################################################################
220
221 cpu_transputer.o: cpu_transputer.c cpu_transputer_instr.c cpu_dyntrans.c \
222 ../memory_rw.c tmp_transputer_head.c tmp_transputer_tail.c
223
224 tmp_transputer_head.c: generate_head
225 ./generate_head transputer Transputer > tmp_transputer_head.c
226
227 tmp_transputer_tail.c: generate_tail
228 ./generate_tail transputer Transputer > tmp_transputer_tail.c
229
230
231 ###############################################################################
232
233 cpu_x86.o: cpu_x86.c cpu_x86_instr.c cpu_dyntrans.c ../memory_rw.c \
234 memory_x86.c tmp_x86_head.c tmp_x86_tail.c
235
236 tmp_x86_head.c: generate_head
237 ./generate_head x86 x86 > tmp_x86_head.c
238
239 tmp_x86_tail.c: generate_tail
240 ./generate_tail x86 x86 > tmp_x86_tail.c
241
242
243 ###############################################################################
244
245 clean:
246 rm -f $(OBJS) $(TOOLS) *core tmp_*.c *.gmon experiment_arm_multi
247
248 clean_all: clean
249 rm -f Makefile
250

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