/[gxemul]/trunk/src/cpus/Makefile.skel
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/cpus/Makefile.skel

Parent Directory Parent Directory | Revision Log Revision Log

Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 6 months ago) by dpavlin
File size: 4758 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.
1 #
2 # $Id: Makefile.skel,v 1.7 2005/09/26 00:08:03 debug Exp $
3 #
4 # Makefile for GXemul src/cpus
5 #
6
7 CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
8
9 OBJS=cpu_mips.o cpu_mips_coproc.o bintrans.o memory_fast_v2h.o $(CPU_ARCHS)
10 TOOLS=generate_head generate_tail $(CPU_TOOLS)
11
12
13 all: $(TOOLS)
14 $(MAKE) buildobjs
15
16
17 buildobjs: $(OBJS)
18
19
20 $(OBJS): Makefile
21
22
23
24 # Old bintrans:
25
26 bintrans.o: bintrans.c bintrans_alpha.c bintrans_i386.c
27
28
29 ###############################################################################
30
31 cpu_alpha.o: cpu_alpha.c cpu_alpha_instr.c cpu_dyntrans.c ../memory_rw.c \
32 tmp_alpha_head.c tmp_alpha_tail.c
33
34 cpu_alpha_instr.c: cpu_alpha_instr_alu.c tmp_alpha_misc.c
35
36 tmp_alpha_misc.c: cpu_alpha_instr_loadstore.c generate_alpha_misc
37 ./generate_alpha_misc > tmp_alpha_misc.c
38
39 tmp_alpha_head.c:
40 ./generate_head alpha Alpha > tmp_alpha_head.c
41
42 tmp_alpha_tail.c:
43 ./generate_tail alpha Alpha > tmp_alpha_tail.c
44
45
46 ###############################################################################
47
48 cpu_arm.o: cpu_arm.c cpu_arm_instr.c cpu_dyntrans.c ../memory_rw.c \
49 tmp_arm_head.c tmp_arm_tail.c
50
51 tmp_arm_loadstore.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
52 ./generate_arm_loadstore > tmp_arm_loadstore.c
53
54 tmp_arm_dpi.c: cpu_arm_instr_dpi.c
55 ./generate_arm_dpi > tmp_arm_dpi.c
56
57 tmp_arm_head.c:
58 ./generate_head arm ARM > tmp_arm_head.c
59
60 tmp_arm_tail.c:
61 ./generate_tail arm ARM > tmp_arm_tail.c
62
63
64 ###############################################################################
65
66 cpu_avr.o: cpu_avr.c cpu_avr_instr.c cpu_dyntrans.c ../memory_rw.c \
67 tmp_avr_head.c tmp_avr_tail.c
68
69 tmp_avr_head.c:
70 ./generate_head avr AVR > tmp_avr_head.c
71
72 tmp_avr_tail.c:
73 ./generate_tail avr AVR > tmp_avr_tail.c
74
75
76 ###############################################################################
77
78 cpu_hppa.o: cpu_hppa.c cpu_hppa_instr.c cpu_dyntrans.c ../memory_rw.c \
79 tmp_hppa_head.c tmp_hppa_tail.c
80
81 tmp_hppa_head.c:
82 ./generate_head hppa HPPA > tmp_hppa_head.c
83
84 tmp_hppa_tail.c:
85 ./generate_tail hppa HPPA > tmp_hppa_tail.c
86
87
88 ###############################################################################
89
90 cpu_i960.o: cpu_i960.c cpu_i960_instr.c cpu_dyntrans.c ../memory_rw.c \
91 tmp_i960_head.c tmp_i960_tail.c
92
93 tmp_i960_head.c:
94 ./generate_head i960 i960 > tmp_i960_head.c
95
96 tmp_i960_tail.c:
97 ./generate_tail i960 i960 > tmp_i960_tail.c
98
99
100 ###############################################################################
101
102 cpu_ia64.o: cpu_ia64.c cpu_ia64_instr.c cpu_dyntrans.c ../memory_rw.c \
103 tmp_ia64_head.c tmp_ia64_tail.c
104
105 tmp_ia64_head.c:
106 ./generate_head ia64 IA64 > tmp_ia64_head.c
107
108 tmp_ia64_tail.c:
109 ./generate_tail ia64 IA64 > tmp_ia64_tail.c
110
111
112 ###############################################################################
113
114 cpu_m68k.o: cpu_m68k.c cpu_m68k_instr.c cpu_dyntrans.c ../memory_rw.c \
115 tmp_m68k_head.c tmp_m68k_tail.c
116
117 tmp_m68k_head.c:
118 ./generate_head m68k M68K > tmp_m68k_head.c
119
120 tmp_m68k_tail.c:
121 ./generate_tail m68k M68K > tmp_m68k_tail.c
122
123
124 ###############################################################################
125
126 cpu_mips.o: cpu_mips.c cpu_mips16.c cpu_dyntrans.c memory_mips.c
127
128 memory_mips.c: ../memory_rw.c memory_mips_v2p.c
129
130
131 ###############################################################################
132
133 cpu_ppc.o: cpu_ppc.c cpu_ppc_instr.c cpu_dyntrans.c memory_ppc.c \
134 ../memory_rw.c tmp_ppc_head.c tmp_ppc_tail.c
135
136 cpu_ppc_instr.c: tmp_ppc_loadstore.c
137
138 tmp_ppc_loadstore.c: cpu_ppc_instr_loadstore.c generate_ppc_loadstore
139 ./generate_ppc_loadstore > tmp_ppc_loadstore.c
140
141 tmp_ppc_head.c:
142 ./generate_head ppc PPC > tmp_ppc_head.c
143
144 tmp_ppc_tail.c:
145 ./generate_tail ppc PPC > tmp_ppc_tail.c
146
147
148 ###############################################################################
149
150 cpu_sh.o: cpu_sh.c cpu_sh_instr.c cpu_dyntrans.c ../memory_rw.c \
151 tmp_sh_head.c tmp_sh_tail.c
152
153 tmp_sh_head.c:
154 ./generate_head sh SH > tmp_sh_head.c
155
156 tmp_sh_tail.c:
157 ./generate_tail sh SH > tmp_sh_tail.c
158
159
160 ###############################################################################
161
162 cpu_sparc.o: cpu_sparc.c cpu_sparc_instr.c cpu_dyntrans.c ../memory_rw.c \
163 tmp_sparc_head.c tmp_sparc_tail.c
164
165 tmp_sparc_head.c:
166 ./generate_head sparc SPARC > tmp_sparc_head.c
167
168 tmp_sparc_tail.c:
169 ./generate_tail sparc SPARC > tmp_sparc_tail.c
170
171
172 ###############################################################################
173
174 cpu_x86.o: cpu_x86.c cpu_x86_instr.c cpu_dyntrans.c ../memory_rw.c \
175 tmp_x86_head.c tmp_x86_tail.c
176
177 memory_x86.c: ../memory_rw.c
178
179 tmp_x86_head.c:
180 ./generate_head x86 x86 > tmp_x86_head.c
181
182 tmp_x86_tail.c:
183 ./generate_tail x86 x86 > tmp_x86_tail.c
184
185
186 ###############################################################################
187
188 clean:
189 rm -f $(OBJS) $(TOOLS) *core tmp_*.c *.gmon
190
191 clean_all: clean
192 rm -f Makefile
193
  ViewVC Help
Powered by ViewVC 1.1.26