/[gxemul]/trunk/src/cpus/Makefile.skel
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Revision 24 - (hide annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File size: 6698 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 dpavlin 14 #
2 dpavlin 24 # $Id: Makefile.skel,v 1.22 2006/06/17 10:49:16 debug Exp $
3 dpavlin 14 #
4     # Makefile for GXemul src/cpus
5     #
6    
7     CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
8    
9 dpavlin 24 OBJS=$(CPU_ARCHS) $(CPU_BACKENDS)
10 dpavlin 14 TOOLS=generate_head generate_tail $(CPU_TOOLS)
11    
12    
13     all: $(TOOLS)
14     $(MAKE) buildobjs
15    
16    
17     buildobjs: $(OBJS)
18    
19    
20     $(OBJS): Makefile
21    
22    
23    
24     ###############################################################################
25    
26     cpu_alpha.o: cpu_alpha.c cpu_alpha_instr.c cpu_dyntrans.c ../memory_rw.c \
27     tmp_alpha_head.c tmp_alpha_tail.c
28    
29     cpu_alpha_instr.c: cpu_alpha_instr_alu.c tmp_alpha_misc.c
30    
31     tmp_alpha_misc.c: cpu_alpha_instr_loadstore.c generate_alpha_misc
32     ./generate_alpha_misc > tmp_alpha_misc.c
33    
34 dpavlin 16 tmp_alpha_head.c: generate_head
35 dpavlin 14 ./generate_head alpha Alpha > tmp_alpha_head.c
36    
37 dpavlin 16 tmp_alpha_tail.c: generate_tail
38 dpavlin 14 ./generate_tail alpha Alpha > tmp_alpha_tail.c
39    
40    
41     ###############################################################################
42    
43     cpu_arm.o: cpu_arm.c cpu_arm_instr.c cpu_dyntrans.c ../memory_rw.c \
44     tmp_arm_head.c tmp_arm_tail.c
45    
46 dpavlin 20 cpu_arm_instr.c: cpu_arm_instr_misc.c
47 dpavlin 18
48 dpavlin 14 tmp_arm_loadstore.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
49     ./generate_arm_loadstore > tmp_arm_loadstore.c
50    
51 dpavlin 18 tmp_arm_multi.c: generate_arm_multi cpu_arm_multi.txt
52     ./generate_arm_multi `cat cpu_arm_multi.txt` > tmp_arm_multi.c
53    
54 dpavlin 16 tmp_arm_dpi.c: cpu_arm_instr_dpi.c generate_arm_dpi
55 dpavlin 14 ./generate_arm_dpi > tmp_arm_dpi.c
56    
57 dpavlin 16 tmp_arm_r0.c: generate_arm_r
58     ./generate_arm_r 0x000 0x0ff > tmp_arm_r0.c
59     tmp_arm_r1.c: generate_arm_r
60     ./generate_arm_r 0x100 0x1ff > tmp_arm_r1.c
61     tmp_arm_r2.c: generate_arm_r
62     ./generate_arm_r 0x200 0x2ff > tmp_arm_r2.c
63     tmp_arm_r3.c: generate_arm_r
64     ./generate_arm_r 0x300 0x3ff > tmp_arm_r3.c
65     tmp_arm_r4.c: generate_arm_r
66     ./generate_arm_r 0x400 0x4ff > tmp_arm_r4.c
67     tmp_arm_r5.c: generate_arm_r
68     ./generate_arm_r 0x500 0x5ff > tmp_arm_r5.c
69     tmp_arm_r6.c: generate_arm_r
70     ./generate_arm_r 0x600 0x6ff > tmp_arm_r6.c
71     tmp_arm_r7.c: generate_arm_r
72     ./generate_arm_r 0x700 0x7ff > tmp_arm_r7.c
73     tmp_arm_r8.c: generate_arm_r
74     ./generate_arm_r 0x800 0x8ff > tmp_arm_r8.c
75     tmp_arm_r9.c: generate_arm_r
76     ./generate_arm_r 0x900 0x9ff > tmp_arm_r9.c
77     tmp_arm_ra.c: generate_arm_r
78     ./generate_arm_r 0xa00 0xaff > tmp_arm_ra.c
79     tmp_arm_rb.c: generate_arm_r
80     ./generate_arm_r 0xb00 0xbff > tmp_arm_rb.c
81     tmp_arm_rc.c: generate_arm_r
82     ./generate_arm_r 0xc00 0xcff > tmp_arm_rc.c
83     tmp_arm_rd.c: generate_arm_r
84     ./generate_arm_r 0xd00 0xdff > tmp_arm_rd.c
85     tmp_arm_re.c: generate_arm_r
86     ./generate_arm_r 0xe00 0xeff > tmp_arm_re.c
87     tmp_arm_rf.c: generate_arm_r
88     ./generate_arm_r 0xf00 0xfff > tmp_arm_rf.c
89    
90     tmp_arm_r.c: generate_arm_r
91     ./generate_arm_r 0 0 > tmp_arm_r.c
92    
93     tmp_arm_head.c: generate_head
94 dpavlin 14 ./generate_head arm ARM > tmp_arm_head.c
95    
96 dpavlin 16 tmp_arm_tail.c: generate_tail
97 dpavlin 14 ./generate_tail arm ARM > tmp_arm_tail.c
98    
99    
100     ###############################################################################
101    
102     cpu_avr.o: cpu_avr.c cpu_avr_instr.c cpu_dyntrans.c ../memory_rw.c \
103     tmp_avr_head.c tmp_avr_tail.c
104    
105 dpavlin 16 tmp_avr_head.c: generate_head
106 dpavlin 14 ./generate_head avr AVR > tmp_avr_head.c
107    
108 dpavlin 16 tmp_avr_tail.c: generate_tail
109 dpavlin 14 ./generate_tail avr AVR > tmp_avr_tail.c
110    
111    
112     ###############################################################################
113    
114     cpu_hppa.o: cpu_hppa.c cpu_hppa_instr.c cpu_dyntrans.c ../memory_rw.c \
115     tmp_hppa_head.c tmp_hppa_tail.c
116    
117 dpavlin 16 tmp_hppa_head.c: generate_head
118 dpavlin 14 ./generate_head hppa HPPA > tmp_hppa_head.c
119    
120 dpavlin 16 tmp_hppa_tail.c: generate_tail
121 dpavlin 14 ./generate_tail hppa HPPA > tmp_hppa_tail.c
122    
123    
124     ###############################################################################
125    
126     cpu_i960.o: cpu_i960.c cpu_i960_instr.c cpu_dyntrans.c ../memory_rw.c \
127     tmp_i960_head.c tmp_i960_tail.c
128    
129 dpavlin 16 tmp_i960_head.c: generate_head
130 dpavlin 14 ./generate_head i960 i960 > tmp_i960_head.c
131    
132 dpavlin 16 tmp_i960_tail.c: generate_tail
133 dpavlin 14 ./generate_tail i960 i960 > tmp_i960_tail.c
134    
135    
136     ###############################################################################
137    
138     cpu_ia64.o: cpu_ia64.c cpu_ia64_instr.c cpu_dyntrans.c ../memory_rw.c \
139     tmp_ia64_head.c tmp_ia64_tail.c
140    
141 dpavlin 16 tmp_ia64_head.c: generate_head
142 dpavlin 14 ./generate_head ia64 IA64 > tmp_ia64_head.c
143    
144 dpavlin 16 tmp_ia64_tail.c: generate_tail
145 dpavlin 14 ./generate_tail ia64 IA64 > tmp_ia64_tail.c
146    
147    
148     ###############################################################################
149    
150     cpu_m68k.o: cpu_m68k.c cpu_m68k_instr.c cpu_dyntrans.c ../memory_rw.c \
151     tmp_m68k_head.c tmp_m68k_tail.c
152    
153 dpavlin 16 tmp_m68k_head.c: generate_head
154 dpavlin 14 ./generate_head m68k M68K > tmp_m68k_head.c
155    
156 dpavlin 16 tmp_m68k_tail.c: generate_tail
157 dpavlin 14 ./generate_tail m68k M68K > tmp_m68k_tail.c
158    
159    
160     ###############################################################################
161    
162 dpavlin 24 cpu_mips.o: cpu_mips.c cpu_dyntrans.c memory_mips.c \
163     cpu_mips_instr.c tmp_mips_loadstore.c tmp_mips_head.c tmp_mips_tail.c
164 dpavlin 14
165     memory_mips.c: ../memory_rw.c memory_mips_v2p.c
166    
167 dpavlin 24 tmp_mips_loadstore.c: cpu_mips_instr_loadstore.c generate_mips_loadstore
168     ./generate_mips_loadstore > tmp_mips_loadstore.c
169    
170 dpavlin 22 tmp_mips_head.c: generate_head
171     ./generate_head mips MIPS > tmp_mips_head.c
172 dpavlin 14
173 dpavlin 22 tmp_mips_tail.c: generate_tail
174     ./generate_tail mips MIPS > tmp_mips_tail.c
175 dpavlin 14
176 dpavlin 20
177     ###############################################################################
178    
179 dpavlin 14 cpu_ppc.o: cpu_ppc.c cpu_ppc_instr.c cpu_dyntrans.c memory_ppc.c \
180 dpavlin 24 ../memory_rw.c tmp_ppc_head.c tmp_ppc_tail.c tmp_ppc_loadstore.c
181 dpavlin 14
182     tmp_ppc_loadstore.c: cpu_ppc_instr_loadstore.c generate_ppc_loadstore
183     ./generate_ppc_loadstore > tmp_ppc_loadstore.c
184    
185 dpavlin 16 tmp_ppc_head.c: generate_head
186 dpavlin 14 ./generate_head ppc PPC > tmp_ppc_head.c
187    
188 dpavlin 16 tmp_ppc_tail.c: generate_tail
189 dpavlin 14 ./generate_tail ppc PPC > tmp_ppc_tail.c
190    
191    
192     ###############################################################################
193    
194     cpu_sh.o: cpu_sh.c cpu_sh_instr.c cpu_dyntrans.c ../memory_rw.c \
195     tmp_sh_head.c tmp_sh_tail.c
196    
197 dpavlin 16 tmp_sh_head.c: generate_head
198 dpavlin 14 ./generate_head sh SH > tmp_sh_head.c
199    
200 dpavlin 16 tmp_sh_tail.c: generate_tail
201 dpavlin 14 ./generate_tail sh SH > tmp_sh_tail.c
202    
203    
204     ###############################################################################
205    
206     cpu_sparc.o: cpu_sparc.c cpu_sparc_instr.c cpu_dyntrans.c ../memory_rw.c \
207     tmp_sparc_head.c tmp_sparc_tail.c
208    
209 dpavlin 16 tmp_sparc_head.c: generate_head
210 dpavlin 14 ./generate_head sparc SPARC > tmp_sparc_head.c
211    
212 dpavlin 16 tmp_sparc_tail.c: generate_tail
213 dpavlin 14 ./generate_tail sparc SPARC > tmp_sparc_tail.c
214    
215    
216     ###############################################################################
217    
218     cpu_x86.o: cpu_x86.c cpu_x86_instr.c cpu_dyntrans.c ../memory_rw.c \
219 dpavlin 20 memory_x86.c tmp_x86_head.c tmp_x86_tail.c
220 dpavlin 14
221 dpavlin 16 tmp_x86_head.c: generate_head
222 dpavlin 14 ./generate_head x86 x86 > tmp_x86_head.c
223    
224 dpavlin 16 tmp_x86_tail.c: generate_tail
225 dpavlin 14 ./generate_tail x86 x86 > tmp_x86_tail.c
226    
227    
228     ###############################################################################
229    
230     clean:
231 dpavlin 18 rm -f $(OBJS) $(TOOLS) *core tmp_*.c *.gmon experiment_arm_multi
232 dpavlin 14
233     clean_all: clean
234     rm -f Makefile
235    

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