/[gxemul]/trunk/src/cpu_sparc.c
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Contents of /trunk/src/cpu_sparc.c

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 6572 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sparc.c,v 1.13 2005/08/16 05:37:10 debug Exp $
29 *
30 * SPARC CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "misc.h"
39
40
41 #ifndef ENABLE_SPARC
42
43
44 #include "cpu_sparc.h"
45
46
47 /*
48 * sparc_cpu_family_init():
49 *
50 * Bogus function.
51 */
52 int sparc_cpu_family_init(struct cpu_family *fp)
53 {
54 return 0;
55 }
56
57
58 #else /* ENABLE_SPARC */
59
60
61 #include "cpu.h"
62 #include "cpu_sparc.h"
63 #include "machine.h"
64 #include "memory.h"
65 #include "symbol.h"
66
67 #define DYNTRANS_DUALMODE_32
68 #define DYNTRANS_32
69 #include "tmp_sparc_head.c"
70
71
72 /*
73 * sparc_cpu_new():
74 *
75 * Create a new SPARC cpu object.
76 *
77 * Returns 1 on success, 0 if there was no matching SPARC processor with
78 * this cpu_type_name.
79 */
80 int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
81 int cpu_id, char *cpu_type_name)
82 {
83 if (strcasecmp(cpu_type_name, "SPARCv9") != 0)
84 return 0;
85
86 cpu->memory_rw = sparc_memory_rw;
87 cpu->update_translation_table = sparc_update_translation_table;
88 cpu->invalidate_translation_caches_paddr =
89 sparc_invalidate_translation_caches_paddr;
90 cpu->invalidate_code_translation_caches =
91 sparc_invalidate_code_translation_caches;
92
93 cpu->byte_order = EMUL_BIG_ENDIAN;
94 cpu->is_32bit = 0;
95
96 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
97 if (cpu_id == 0) {
98 debug("%s", cpu->name);
99 }
100
101 return 1;
102 }
103
104
105 /*
106 * sparc_cpu_list_available_types():
107 *
108 * Print a list of available SPARC CPU types.
109 */
110 void sparc_cpu_list_available_types(void)
111 {
112 debug("SPARCv9\n");
113 /* TODO */
114 }
115
116
117 /*
118 * sparc_cpu_dumpinfo():
119 */
120 void sparc_cpu_dumpinfo(struct cpu *cpu)
121 {
122 debug("\n");
123 /* TODO */
124 }
125
126
127 /*
128 * sparc_cpu_register_dump():
129 *
130 * Dump cpu registers in a relatively readable format.
131 *
132 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
133 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
134 */
135 void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
136 {
137 char *symbol;
138 uint64_t offset, tmp;
139 int i, x = cpu->cpu_id;
140 int bits32 = 0;
141
142 if (gprs) {
143 /* Special registers (pc, ...) first: */
144 symbol = get_symbol_name(&cpu->machine->symbol_context,
145 cpu->pc, &offset);
146
147 debug("cpu%i: pc = 0x", x);
148 if (bits32)
149 debug("%08x", (int)cpu->pc);
150 else
151 debug("%016llx", (long long)cpu->pc);
152 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
153
154 /* TODO */
155 }
156 }
157
158
159 /*
160 * sparc_cpu_register_match():
161 */
162 void sparc_cpu_register_match(struct machine *m, char *name,
163 int writeflag, uint64_t *valuep, int *match_register)
164 {
165 int cpunr = 0;
166
167 /* CPU number: */
168
169 /* TODO */
170
171 /* Register name: */
172 if (strcasecmp(name, "pc") == 0) {
173 if (writeflag) {
174 m->cpus[cpunr]->pc = *valuep;
175 } else
176 *valuep = m->cpus[cpunr]->pc;
177 *match_register = 1;
178 }
179 }
180
181
182 /*
183 * sparc_cpu_show_full_statistics():
184 *
185 * Show detailed statistics on opcode usage on each cpu.
186 */
187 void sparc_cpu_show_full_statistics(struct machine *m)
188 {
189 fatal("sparc_cpu_show_full_statistics(): TODO\n");
190 }
191
192
193 /*
194 * sparc_cpu_tlbdump():
195 *
196 * Called from the debugger to dump the TLB in a readable format.
197 * x is the cpu number to dump, or -1 to dump all CPUs.
198 *
199 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
200 * just dumped.
201 */
202 void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag)
203 {
204 fatal("sparc_cpu_tlbdump(): TODO\n");
205 }
206
207
208 /*
209 * sparc_cpu_interrupt():
210 */
211 int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
212 {
213 fatal("sparc_cpu_interrupt(): TODO\n");
214 return 0;
215 }
216
217
218 /*
219 * sparc_cpu_interrupt_ack():
220 */
221 int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
222 {
223 /* fatal("sparc_cpu_interrupt_ack(): TODO\n"); */
224 return 0;
225 }
226
227
228 /*
229 * sparc_cpu_disassemble_instr():
230 *
231 * Convert an instruction word into human readable format, for instruction
232 * tracing.
233 *
234 * If running is 1, cpu->pc should be the address of the instruction.
235 *
236 * If running is 0, things that depend on the runtime environment (eg.
237 * register contents) will not be shown, and addr will be used instead of
238 * cpu->pc for relative addresses.
239 */
240 int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
241 int running, uint64_t dumpaddr, int bintrans)
242 {
243 uint64_t offset, addr;
244 uint32_t iword;
245 int hi6;
246 char *symbol, *mnem = "ERROR";
247
248 if (running)
249 dumpaddr = cpu->pc;
250
251 symbol = get_symbol_name(&cpu->machine->symbol_context,
252 dumpaddr, &offset);
253 if (symbol != NULL && offset==0)
254 debug("<%s>\n", symbol);
255
256 if (cpu->machine->ncpus > 1 && running)
257 debug("cpu%i: ", cpu->cpu_id);
258
259 /* if (cpu->cd.sparc.bits == 32)
260 debug("%08x", (int)dumpaddr);
261 else
262 */ debug("%016llx", (long long)dumpaddr);
263
264 iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
265 + instr[3];
266
267 debug(": %08x\t", iword);
268
269 /*
270 * Decode the instruction:
271 */
272
273 hi6 = iword >> 26;
274
275 switch (hi6) {
276 default:
277 /* TODO */
278 debug("unimplemented hi6 = 0x%02x", hi6);
279 }
280
281 debug("\n");
282 return sizeof(iword);
283 }
284
285
286 #include "tmp_sparc_tail.c"
287
288
289 #endif /* ENABLE_SPARC */

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