--- trunk/src/cpu_mips.c	2007/10/08 16:17:52	3
+++ trunk/src/cpu_mips.c	2007/10/08 16:18:00	4
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_mips.c,v 1.34 2005/03/20 20:27:26 debug Exp $
+ *  $Id: cpu_mips.c,v 1.39 2005/04/15 21:39:59 debug Exp $
  *
  *  MIPS core CPU emulation.
  */
@@ -728,6 +728,9 @@
 	if (running)
 		dumpaddr = cpu->pc;
 
+	if ((dumpaddr & 3) != 0)
+		printf("WARNING: Unaligned address!\n");
+
 	symbol = get_symbol_name(&cpu->machine->symbol_context,
 	    dumpaddr, &offset);
 	if (symbol != NULL && offset==0)
@@ -1608,10 +1611,12 @@
 
 	if (tlb && vaddr < 0x1000) {
 		uint64_t offset;
-		char *symbol = get_symbol_name(
-		    &cpu->machine->symbol_context, cpu->cd.mips.pc_last, &offset);
-		fatal("warning: LOW reference vaddr=0x%08x, exception %s, pc=%08llx <%s>\n",
-		    (int)vaddr, exception_names[exccode], (long long)cpu->cd.mips.pc_last, symbol? symbol : "(no symbol)");
+		char *symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->cd.mips.pc_last, &offset);
+		fatal("[ warning: LOW reference vaddr=0x%08x, exception %s, "
+		    "pc=%08llx <%s> ]\n", (int)vaddr, exception_names[exccode],
+		    (long long)cpu->cd.mips.pc_last,
+		    symbol? symbol : "(no symbol)");
 	}
 
 	/*  Clear the exception code bits of the cause register...  */
@@ -2116,29 +2121,7 @@
 
 
 #ifdef BINTRANS
-        /*  Caches are not very coozy to handle in bintrans:  */
-        switch (cpu->cd.mips.cpu_type.mmu_model) {
-        case MMU3K:
-                if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) {
-			/*  cpu->cd.mips.dont_run_next_bintrans = 1;  */
-			cpu->cd.mips.vaddr_to_hostaddr_table0 =
-			    cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_SWAP_CACHES?
-			       cpu->cd.mips.vaddr_to_hostaddr_table0_cacheisol_i
-			     : cpu->cd.mips.vaddr_to_hostaddr_table0_cacheisol_d;
-		} else {
-			cpu->cd.mips.vaddr_to_hostaddr_table0 =
-			    cpu->cd.mips.vaddr_to_hostaddr_table0_kernel;
-
-			/*  TODO: cpu->cd.mips.vaddr_to_hostaddr_table0_user;  */
-		}
-                break;
-	default:
-		cpu->cd.mips.vaddr_to_hostaddr_table0 =
-		    cpu->cd.mips.vaddr_to_hostaddr_table0_kernel;
-		/*  TODO: cpu->cd.mips.vaddr_to_hostaddr_table0_user;  */
-        }
-
-	if ((single_step || cpu->machine->instruction_trace)
+	if ((single_step || instruction_trace_cached)
 	    && cpu->machine->bintrans_enable)
 		cpu->cd.mips.dont_run_next_bintrans = 1;
 #endif
@@ -2288,7 +2271,6 @@
 					res &= BINTRANS_N_MASK;
 
 					if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
-						/*  TODO: 32-bit or 64-bit?  */
 						int x = cp0->reg[COP0_COUNT], y = cp0->reg[COP0_COMPARE];
 						int diff = x - y;
 						if (diff < 0 && diff + (res-1) >= 0
@@ -3329,7 +3311,9 @@
 					 *  (This cache-line was written to by
 					 *  someone else.)
 					 */
-					if (cpu->cd.mips.rmw == 0) {
+					if (cpu->cd.mips.rmw == 0 ||
+					    cpu->cd.mips.rmw_addr != addr ||
+					    cpu->cd.mips.rmw_len != wlen) {
 						/*  The store failed:  */
 						cpu->cd.mips.gpr[rt] = 0;
 						if (instruction_trace_cached)