--- trunk/src/cpu_mips.c	2007/10/08 16:18:22	9
+++ trunk/src/cpu_mips.c	2007/10/08 16:18:27	10
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_mips.c,v 1.42 2005/06/11 20:59:11 debug Exp $
+ *  $Id: cpu_mips.c,v 1.46 2005/06/26 22:23:42 debug Exp $
  *
  *  MIPS core CPU emulation.
  */
@@ -113,11 +113,11 @@
 	ch[3] = ch[2] = '\0';
 
 	if (r<0 || r>=32)
-		strcpy(ch, "xx");
+		strlcpy(ch, "xx", sizeof(ch));
 	else if (machine->show_symbolic_register_names)
-		strcpy(ch, regnames[r]);
+		strlcpy(ch, regnames[r], sizeof(ch));
 	else
-		sprintf(ch, "r%i", r);
+		snprintf(ch, sizeof(ch), "r%i", r);
 
 	return ch;
 }
@@ -127,11 +127,13 @@
  *  mips_cpu_new():
  *
  *  Create a new MIPS cpu object.
+ *
+ *  Returns 1 on success, 0 if there was no valid MIPS processor with
+ *  a matching name.
  */
-struct cpu *mips_cpu_new(struct memory *mem, struct machine *machine,
+int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
 	int cpu_id, char *cpu_type_name)
 {
-	struct cpu *cpu;
 	int i, found, j, tags_size, n_cache_lines, size_per_cache_line;
 	struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS;
 	int64_t secondary_cache_size;
@@ -149,24 +151,12 @@
 	}
 
 	if (found == -1)
-		return NULL;
-
-	cpu = malloc(sizeof(struct cpu));
-	if (cpu == NULL) {
-		fprintf(stderr, "out of memory\n");
-		exit(1);
-	}
+		return 0;
 
-	memset(cpu, 0, sizeof(struct cpu));
 	cpu->memory_rw          = mips_memory_rw;
 	cpu->cd.mips.cpu_type   = cpu_type_defs[found];
 	cpu->name               = cpu->cd.mips.cpu_type.name;
-	cpu->mem                = mem;
-	cpu->machine            = machine;
-	cpu->cpu_id             = cpu_id;
 	cpu->byte_order         = EMUL_LITTLE_ENDIAN;
-	cpu->bootstrap_cpu_flag = 0;
-	cpu->running            = 0;
 	cpu->cd.mips.gpr[MIPS_GPR_SP]	= INITIAL_STACK_POINTER;
 
 	if (cpu_id == 0)
@@ -339,7 +329,7 @@
 			cpu->translate_address = translate_address_generic;
 	}
 
-	return cpu;
+	return 1;
 }
 
 
@@ -663,7 +653,7 @@
 				if (writeflag) {
 					coproc_register_write(m->cpus[cpunr],
 					    m->cpus[cpunr]->cd.mips.coproc[0], nr,
-					    valuep, 1);
+					    valuep, 1, 0);
 				} else {
 					/*  TODO: Use coproc_register_read instead?  */
 					*valuep = m->cpus[cpunr]->cd.mips.coproc[0]->reg[nr];
@@ -1988,27 +1978,27 @@
 
 
 	/*
-	 *  ROM emulation:
+	 *  ROM emulation:  (0xbfcXXXXX or 0x9fcXXXXX)
 	 *
 	 *  This assumes that a jal was made to a ROM address,
 	 *  and we should return via gpr ra.
 	 */
-	if ((cached_pc & 0xfff00000) == 0xbfc00000 &&
+	if ((cached_pc & 0xdff00000) == 0x9fc00000 &&
 	    cpu->machine->prom_emulation) {
-		int rom_jal, res = 1;
+		int rom_jal = 1, res = 1;
 		switch (cpu->machine->machine_type) {
 		case MACHINE_DEC:
 			res = decstation_prom_emul(cpu);
-			rom_jal = 1;
 			break;
 		case MACHINE_PS2:
 			res = playstation2_sifbios_emul(cpu);
-			rom_jal = 1;
 			break;
 		case MACHINE_ARC:
 		case MACHINE_SGI:
 			res = arcbios_emul(cpu);
-			rom_jal = 1;
+			break;
+		case MACHINE_EVBMIPS:
+			res = yamon_emul(cpu);
 			break;
 		default:
 			rom_jal = 0;
@@ -3379,15 +3369,15 @@
 								    !(cp0->reg[COP0_STATUS] & STATUS_FR))) {
 									uint64_t a, b;
 									coproc_register_read(cpu,
-									    cpu->cd.mips.coproc[cpnr], rt, &a);
+									    cpu->cd.mips.coproc[cpnr], rt, &a, 0);
 									coproc_register_read(cpu,
-									    cpu->cd.mips.coproc[cpnr], rt^1, &b);
+									    cpu->cd.mips.coproc[cpnr], rt^1, &b, 0);
 									if (rt & 1)
 										fatal("WARNING: SDCx in 32-bit mode from odd register!\n");
 									value = (a & 0xffffffffULL)
 									    | (b << 32);
 								} else
-									coproc_register_read(cpu, cpu->cd.mips.coproc[cpnr], rt, &value);
+									coproc_register_read(cpu, cpu->cd.mips.coproc[cpnr], rt, &value, 0);
 							}
 							break;
 					default:
@@ -3524,16 +3514,16 @@
 								b = (int64_t)(int32_t) (value >> 32);
 								coproc_register_write(cpu,
 								    cpu->cd.mips.coproc[cpnr], rt, &a,
-								    hi6==HI6_LDC1 || hi6==HI6_LDC2);
+								    hi6==HI6_LDC1 || hi6==HI6_LDC2, 0);
 								coproc_register_write(cpu,
 								    cpu->cd.mips.coproc[cpnr], rt ^ 1, &b,
-								    hi6==HI6_LDC1 || hi6==HI6_LDC2);
+								    hi6==HI6_LDC1 || hi6==HI6_LDC2, 0);
 								if (rt & 1)
 									fatal("WARNING: LDCx in 32-bit mode to odd register!\n");
 							} else {
 								coproc_register_write(cpu,
 								    cpu->cd.mips.coproc[cpnr], rt, &value,
-								    hi6==HI6_LDC1 || hi6==HI6_LDC2);
+								    hi6==HI6_LDC1 || hi6==HI6_LDC2, 0);
 							}
 						}
 						break;