/[gxemul]/trunk/src/cpu_arm_instr_loadstore.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/cpu_arm_instr_loadstore.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 6447 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_arm_instr_loadstore.c,v 1.7 2005/08/16 05:37:10 debug Exp $
29 *
30 *
31 * TODO: Native load/store if the endianness is the same as the host's
32 * (and check for alignment?)
33 */
34
35 #ifdef A__REG
36 void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic) { }
37 void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
38 {fatal("TODO: blah...\n");}
39
40
41 #else /* !A__REG */
42
43
44 void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic)
45 {
46 #ifdef A__B
47 unsigned char data[1];
48 #else
49 unsigned char data[4];
50 #endif
51 uint32_t addr;
52
53 addr = *((uint32_t *)ic->arg[0])
54 #ifdef A__P
55 #ifdef A__U
56 +
57 #else
58 -
59 #endif
60 #ifdef A__FIXINC
61 A__FIXINC;
62 #else
63 ic->arg[1];
64 #endif
65 #endif
66 ;
67
68 #ifdef A__L
69 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
70 MEM_READ, CACHE_DATA)) {
71 fatal("load failed: TODO\n");
72 exit(1);
73 }
74 #ifdef A__B
75 *((uint32_t *)ic->arg[2]) = data[0];
76 #else
77 *((uint32_t *)ic->arg[2]) = data[0] + (data[1] << 8) +
78 (data[2] << 16) + (data[3] << 24);
79 #endif
80 #else
81 #ifdef A__B
82 data[0] = *((uint32_t *)ic->arg[2]);
83 #else
84 data[0] = (*((uint32_t *)ic->arg[2]));
85 data[1] = (*((uint32_t *)ic->arg[2])) >> 8;
86 data[2] = (*((uint32_t *)ic->arg[2])) >> 16;
87 data[3] = (*((uint32_t *)ic->arg[2])) >> 24;
88 #endif
89 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
90 MEM_WRITE, CACHE_DATA)) {
91 fatal("store failed: TODO\n");
92 exit(1);
93 }
94 #endif
95
96 #ifdef A__P
97 #ifdef A__W
98 *((uint32_t *)ic->arg[0]) = addr;
99 #endif
100 #else /* post-index writeback */
101 *((uint32_t *)ic->arg[0]) = addr
102 #ifdef A__U
103 +
104 #else
105 -
106 #endif
107 #ifdef A__FIXINC
108 A__FIXINC;
109 #else
110 ic->arg[1];
111 #endif
112 #endif
113 }
114
115 void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
116 {
117 uint32_t addr = *((uint32_t *)ic->arg[0])
118 #ifdef A__P
119 #ifdef A__U
120 +
121 #else
122 -
123 #endif
124 #ifdef A__FIXINC
125 A__FIXINC
126 #else
127 ic->arg[1]
128 #endif
129 #endif
130 ;
131 unsigned char *page = cpu->cd.arm.
132 #ifdef A__L
133 host_load
134 #else
135 host_store
136 #endif
137 [addr >> 12];
138
139 if (page == NULL) {
140 A__NAME__general(cpu, ic);
141 } else {
142 #ifdef A__P
143 #ifdef A__W
144 *((uint32_t *)ic->arg[0]) = addr;
145 #endif
146 #else /* post-index writeback */
147 *((uint32_t *)ic->arg[0]) = addr
148 #ifdef A__U
149 +
150 #else
151 -
152 #endif
153 #ifdef A__FIXINC
154 A__FIXINC;
155 #else
156 ic->arg[1];
157 #endif
158 #endif
159
160 #ifdef A__L
161 #ifdef A__B
162 *((uint32_t *)ic->arg[2]) = page[addr & 4095];
163 #else
164 addr &= 4095;
165 *((uint32_t *)ic->arg[2]) = page[addr] +
166 (page[addr + 1] << 8) +
167 (page[addr + 2] << 16) +
168 (page[addr + 3] << 24);
169 #endif
170 #else
171 #ifdef A__B
172 page[addr & 4095] = *((uint32_t *)ic->arg[2]);
173 #else
174 addr &= 4095;
175 page[addr] = *((uint32_t *)ic->arg[2]);
176 page[addr+1] = (*((uint32_t *)ic->arg[2])) >> 8;
177 page[addr+2] = (*((uint32_t *)ic->arg[2])) >> 16;
178 page[addr+3] = (*((uint32_t *)ic->arg[2])) >> 24;
179 #endif
180 #endif
181 }
182 }
183 #endif
184
185 #ifndef A__NOCONDITIONS
186 void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
187 { if (cpu->cd.arm.flags & ARM_FLAG_Z) A__NAME(cpu, ic); }
188 void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
189 { if (!(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); }
190 void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
191 { if (cpu->cd.arm.flags & ARM_FLAG_C) A__NAME(cpu, ic); }
192 void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
193 { if (!(cpu->cd.arm.flags & ARM_FLAG_C)) A__NAME(cpu, ic); }
194 void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
195 { if (cpu->cd.arm.flags & ARM_FLAG_N) A__NAME(cpu, ic); }
196 void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
197 { if (!(cpu->cd.arm.flags & ARM_FLAG_N)) A__NAME(cpu, ic); }
198 void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
199 { if (cpu->cd.arm.flags & ARM_FLAG_V) A__NAME(cpu, ic); }
200 void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
201 { if (!(cpu->cd.arm.flags & ARM_FLAG_V)) A__NAME(cpu, ic); }
202
203 void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
204 { if (cpu->cd.arm.flags & ARM_FLAG_C &&
205 !(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); }
206 void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
207 { if (cpu->cd.arm.flags & ARM_FLAG_Z &&
208 !(cpu->cd.arm.flags & ARM_FLAG_C)) A__NAME(cpu, ic); }
209 void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
210 { if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) ==
211 ((cpu->cd.arm.flags & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); }
212 void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
213 { if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) !=
214 ((cpu->cd.arm.flags & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); }
215 void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
216 { if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) ==
217 ((cpu->cd.arm.flags & ARM_FLAG_V)?1:0) &&
218 !(cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); }
219 void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
220 { if (((cpu->cd.arm.flags & ARM_FLAG_N)?1:0) !=
221 ((cpu->cd.arm.flags & ARM_FLAG_V)?1:0) ||
222 (cpu->cd.arm.flags & ARM_FLAG_Z)) A__NAME(cpu, ic); }
223 #endif

  ViewVC Help
Powered by ViewVC 1.1.26