/[gxemul]/trunk/src/cpu_arm_instr_cmps.c
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Contents of /trunk/src/cpu_arm_instr_cmps.c

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 4128 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_arm_instr_cmps.c,v 1.1 2005/06/30 20:41:28 debug Exp $
29 */
30
31 #ifndef CPU_ARM_INSTR_CMPS
32 #define CPU_ARM_INSTR_CMPS
33
34 #define A__NAME arm_instr_cmps_r0_0
35 #define A__Rn 0
36 #include "cpu_arm_instr_cmps.c"
37 #undef A__Rn
38 #undef A__NAME
39
40 #define A__NAME arm_instr_cmps_r1_0
41 #define A__Rn 1
42 #include "cpu_arm_instr_cmps.c"
43 #undef A__Rn
44 #undef A__NAME
45
46 #define A__NAME arm_instr_cmps_r2_0
47 #define A__Rn 2
48 #include "cpu_arm_instr_cmps.c"
49 #undef A__Rn
50 #undef A__NAME
51
52 #define A__NAME arm_instr_cmps_r3_0
53 #define A__Rn 3
54 #include "cpu_arm_instr_cmps.c"
55 #undef A__Rn
56 #undef A__NAME
57
58 #define A__NAME arm_instr_cmps_r4_0
59 #define A__Rn 4
60 #include "cpu_arm_instr_cmps.c"
61 #undef A__Rn
62 #undef A__NAME
63
64 #define A__NAME arm_instr_cmps_r5_0
65 #define A__Rn 5
66 #include "cpu_arm_instr_cmps.c"
67 #undef A__Rn
68 #undef A__NAME
69
70 #define A__NAME arm_instr_cmps_r6_0
71 #define A__Rn 6
72 #include "cpu_arm_instr_cmps.c"
73 #undef A__Rn
74 #undef A__NAME
75
76 #define A__NAME arm_instr_cmps_r7_0
77 #define A__Rn 7
78 #include "cpu_arm_instr_cmps.c"
79 #undef A__Rn
80 #undef A__NAME
81
82 #define A__NAME arm_instr_cmps_r8_0
83 #define A__Rn 8
84 #include "cpu_arm_instr_cmps.c"
85 #undef A__Rn
86 #undef A__NAME
87
88 #define A__NAME arm_instr_cmps_r9_0
89 #define A__Rn 9
90 #include "cpu_arm_instr_cmps.c"
91 #undef A__Rn
92 #undef A__NAME
93
94 #define A__NAME arm_instr_cmps_r10_0
95 #define A__Rn 10
96 #include "cpu_arm_instr_cmps.c"
97 #undef A__Rn
98 #undef A__NAME
99
100 #define A__NAME arm_instr_cmps_r11_0
101 #define A__Rn 11
102 #include "cpu_arm_instr_cmps.c"
103 #undef A__Rn
104 #undef A__NAME
105
106 #define A__NAME arm_instr_cmps_r12_0
107 #define A__Rn 12
108 #include "cpu_arm_instr_cmps.c"
109 #undef A__Rn
110 #undef A__NAME
111
112 #define A__NAME arm_instr_cmps_r13_0
113 #define A__Rn 13
114 #include "cpu_arm_instr_cmps.c"
115 #undef A__Rn
116 #undef A__NAME
117
118 #define A__NAME arm_instr_cmps_r14_0
119 #define A__Rn 14
120 #include "cpu_arm_instr_cmps.c"
121 #undef A__Rn
122 #undef A__NAME
123
124 void (*arm_cmps_0[15])(struct cpu *, struct arm_instr_call *) = {
125 arm_instr_cmps_r0_0, arm_instr_cmps_r1_0,
126 arm_instr_cmps_r2_0, arm_instr_cmps_r3_0,
127 arm_instr_cmps_r4_0, arm_instr_cmps_r5_0,
128 arm_instr_cmps_r6_0, arm_instr_cmps_r7_0,
129 arm_instr_cmps_r8_0, arm_instr_cmps_r9_0,
130 arm_instr_cmps_r10_0, arm_instr_cmps_r11_0,
131 arm_instr_cmps_r12_0, arm_instr_cmps_r13_0,
132 arm_instr_cmps_r14_0 };
133
134 #else
135
136 void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
137 {
138 uint32_t a = cpu->cd.arm.r[A__Rn];
139 cpu->cd.arm.flags &=
140 ~(ARM_FLAG_Z | ARM_FLAG_N | ARM_FLAG_V | ARM_FLAG_C);
141 if (a != 0)
142 cpu->cd.arm.flags |= ARM_FLAG_C;
143 else
144 cpu->cd.arm.flags |= ARM_FLAG_Z;
145 if ((int32_t)a < 0)
146 cpu->cd.arm.flags |= ARM_FLAG_N;
147 }
148
149 #endif

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