25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.19 2005/06/27 16:44:54 debug Exp $ |
* $Id: cpu_arm.c,v 1.57 2005/08/12 20:20:28 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
32 |
* Whenever there is a reference to "(1)", that means |
* Sources of information refered to in cpu_arm*.c: |
33 |
* "http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html". |
* |
34 |
|
* (1) http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html |
35 |
*/ |
*/ |
36 |
|
|
37 |
#include <stdio.h> |
#include <stdio.h> |
68 |
#include "memory.h" |
#include "memory.h" |
69 |
#include "symbol.h" |
#include "symbol.h" |
70 |
|
|
71 |
|
#define DYNTRANS_32 |
72 |
|
#include "tmp_arm_head.c" |
73 |
|
|
|
/* instr uses the same names as in cpu_arm_instr.c */ |
|
|
#define instr(n) arm_instr_ ## n |
|
74 |
|
|
75 |
static char *arm_condition_string[16] = { |
/* ARM symbolic register names and condition strings: */ |
76 |
"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
static char *arm_regname[N_ARM_REGS] = ARM_REG_NAMES; |
77 |
"hi", "ls", "ge", "lt", "gt", "le", ""/*Always*/, "(INVALID)" }; |
static char *arm_condition_string[16] = ARM_CONDITION_STRINGS; |
78 |
|
|
79 |
/* ARM symbolic register names: */ |
/* Data Processing Instructions: */ |
80 |
static char *arm_regname[N_ARM_REGS] = { |
static char *arm_dpiname[16] = ARM_DPI_NAMES; |
81 |
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 }; |
82 |
"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }; |
static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 }; |
|
|
|
|
/* Data processing instructions: */ |
|
|
static char *arm_dpiname[16] = { |
|
|
"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
|
|
"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }; |
|
|
static int arm_dpi_uses_d[16] = { |
|
|
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1 }; |
|
|
static int arm_dpi_uses_n[16] = { |
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0 }; |
|
|
|
|
|
extern volatile int single_step; |
|
|
extern int old_show_trace_tree; |
|
|
extern int old_instruction_trace; |
|
|
extern int old_quiet_mode; |
|
|
extern int quiet_mode; |
|
83 |
|
|
84 |
|
|
85 |
/* |
/* |
86 |
* arm_cpu_new(): |
* arm_cpu_new(): |
87 |
* |
* |
88 |
* Create a new ARM cpu object by filling in the CPU struct. |
* Create a new ARM cpu object by filling the CPU struct. |
89 |
* Return 1 on success, 0 if cpu_type_name isn't a valid ARM processor. |
* Return 1 on success, 0 if cpu_type_name isn't a valid ARM processor. |
90 |
*/ |
*/ |
91 |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
95 |
return 0; |
return 0; |
96 |
|
|
97 |
cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
98 |
|
cpu->update_translation_table = arm_update_translation_table; |
99 |
|
cpu->invalidate_translation_caches_paddr = |
100 |
|
arm_invalidate_translation_caches_paddr; |
101 |
|
cpu->invalidate_code_translation_caches = |
102 |
|
arm_invalidate_code_translation_caches; |
103 |
|
cpu->is_32bit = 1; |
104 |
|
|
105 |
cpu->cd.arm.flags = ARM_FLAG_I | ARM_FLAG_F | ARM_MODE_USR32; |
cpu->cd.arm.flags = ARM_FLAG_I | ARM_FLAG_F | ARM_MODE_USR32; |
106 |
|
|
118 |
*/ |
*/ |
119 |
void arm_cpu_dumpinfo(struct cpu *cpu) |
void arm_cpu_dumpinfo(struct cpu *cpu) |
120 |
{ |
{ |
121 |
debug(" (%i MB translation cache)\n", |
/* TODO */ |
122 |
(int)(ARM_TRANSLATION_CACHE_SIZE / 1048576)); |
debug("\n"); |
123 |
} |
} |
124 |
|
|
125 |
|
|
175 |
{ |
{ |
176 |
char *symbol; |
char *symbol; |
177 |
uint64_t offset; |
uint64_t offset; |
178 |
|
int mode = cpu->cd.arm.flags & ARM_FLAG_MODE; |
179 |
int i, x = cpu->cpu_id; |
int i, x = cpu->cpu_id; |
180 |
|
|
181 |
if (gprs) { |
if (gprs) { |
189 |
(cpu->cd.arm.flags & ARM_FLAG_V)? "V" : "v", |
(cpu->cd.arm.flags & ARM_FLAG_V)? "V" : "v", |
190 |
(cpu->cd.arm.flags & ARM_FLAG_I)? "I" : "i", |
(cpu->cd.arm.flags & ARM_FLAG_I)? "I" : "i", |
191 |
(cpu->cd.arm.flags & ARM_FLAG_F)? "F" : "f"); |
(cpu->cd.arm.flags & ARM_FLAG_F)? "F" : "f"); |
192 |
debug(" pc = 0x%08x", (int)cpu->cd.arm.r[ARM_PC]); |
if (mode < ARM_MODE_USR32) |
193 |
|
debug(" pc = 0x%07x", |
194 |
|
(int)(cpu->cd.arm.r[ARM_PC] & 0x03ffffff)); |
195 |
|
else |
196 |
|
debug(" pc = 0x%08x", (int)cpu->cd.arm.r[ARM_PC]); |
197 |
|
|
198 |
/* TODO: Flags */ |
/* TODO: Flags */ |
199 |
|
|
213 |
|
|
214 |
|
|
215 |
/* |
/* |
216 |
|
* arm_cpu_show_full_statistics(): |
217 |
|
* |
218 |
|
* Show detailed statistics on opcode usage on each cpu. |
219 |
|
*/ |
220 |
|
void arm_cpu_show_full_statistics(struct machine *m) |
221 |
|
{ |
222 |
|
fatal("arm_cpu_show_full_statistics(): TODO\n"); |
223 |
|
} |
224 |
|
|
225 |
|
|
226 |
|
/* |
227 |
|
* arm_cpu_tlbdump(): |
228 |
|
* |
229 |
|
* Called from the debugger to dump the TLB in a readable format. |
230 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
231 |
|
* |
232 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
233 |
|
* just dumped. |
234 |
|
*/ |
235 |
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
236 |
|
{ |
237 |
|
fatal("arm_cpu_tlbdump(): TODO\n"); |
238 |
|
} |
239 |
|
|
240 |
|
|
241 |
|
/* |
242 |
|
* arm_cpu_interrupt(): |
243 |
|
*/ |
244 |
|
int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
245 |
|
{ |
246 |
|
fatal("arm_cpu_interrupt(): TODO\n"); |
247 |
|
return 0; |
248 |
|
} |
249 |
|
|
250 |
|
|
251 |
|
/* |
252 |
|
* arm_cpu_interrupt_ack(): |
253 |
|
*/ |
254 |
|
int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
255 |
|
{ |
256 |
|
/* fatal("arm_cpu_interrupt_ack(): TODO\n"); */ |
257 |
|
return 0; |
258 |
|
} |
259 |
|
|
260 |
|
|
261 |
|
/* |
262 |
* arm_cpu_disassemble_instr(): |
* arm_cpu_disassemble_instr(): |
263 |
* |
* |
264 |
* Convert an instruction word into human readable format, for instruction |
* Convert an instruction word into human readable format, for instruction |
275 |
{ |
{ |
276 |
uint32_t iw, tmp; |
uint32_t iw, tmp; |
277 |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
278 |
int p_bit, u_bit, b_bit, w_bit, l_bit; |
int i, n, p_bit, u_bit, b_bit, w_bit, l_bit; |
279 |
char *symbol, *condition; |
char *symbol, *condition; |
280 |
uint64_t offset; |
uint64_t offset; |
281 |
|
|
319 |
* xxxx000a aaaSnnnn ddddcccc ctttmmmm Register form |
* xxxx000a aaaSnnnn ddddcccc ctttmmmm Register form |
320 |
* xxxx001a aaaSnnnn ddddrrrr bbbbbbbb Immediate form |
* xxxx001a aaaSnnnn ddddrrrr bbbbbbbb Immediate form |
321 |
*/ |
*/ |
322 |
if (iw & 0x80 && !(main_opcode & 2)) { |
if (iw & 0x80 && !(main_opcode & 2) && iw & 0x10) { |
323 |
debug("UNIMPLEMENTED reg (c!=0)\n"); |
debug("UNIMPLEMENTED reg (c!=0), t odd\n"); |
324 |
break; |
break; |
325 |
} |
} |
326 |
|
|
348 |
debug("%s", arm_regname[iw & 15]); |
debug("%s", arm_regname[iw & 15]); |
349 |
switch (t) { |
switch (t) { |
350 |
case 0: if (c != 0) |
case 0: if (c != 0) |
351 |
debug(" LSL #%i", c); |
debug(", lsl #%i", c); |
352 |
break; |
break; |
353 |
case 1: debug(" LSL %s", arm_regname[c >> 1]); |
case 1: debug(", lsl %s", arm_regname[c >> 1]); |
354 |
break; |
break; |
355 |
case 2: debug(" LSR #%i", c? c : 32); |
case 2: debug(", lsr #%i", c? c : 32); |
356 |
break; |
break; |
357 |
case 3: debug(" LSR %s", arm_regname[c >> 1]); |
case 3: debug(", lsr %s", arm_regname[c >> 1]); |
358 |
break; |
break; |
359 |
case 4: debug(" ASR #%i", c? c : 32); |
case 4: debug(", asr #%i", c? c : 32); |
360 |
break; |
break; |
361 |
case 5: debug(" ASR %s", arm_regname[c >> 1]); |
case 5: debug(", asr %s", arm_regname[c >> 1]); |
362 |
break; |
break; |
363 |
case 6: if (c != 0) |
case 6: if (c != 0) |
364 |
debug(" ROR #%i", c); |
debug(", ror #%i", c); |
365 |
else |
else |
366 |
debug(" RRX"); |
debug(", rrx"); |
367 |
break; |
break; |
368 |
case 7: debug(" ROR %s", arm_regname[c >> 1]); |
case 7: debug(", ror %s", arm_regname[c >> 1]); |
369 |
break; |
break; |
370 |
} |
} |
371 |
} |
} |
406 |
break; |
break; |
407 |
case 0x8: /* Block Data Transfer */ |
case 0x8: /* Block Data Transfer */ |
408 |
case 0x9: |
case 0x9: |
409 |
debug("TODO: block data transfer\n"); |
/* See (1): xxxx100P USWLnnnn llllllll llllllll */ |
410 |
|
p_bit = main_opcode & 1; |
411 |
|
s_bit = b_bit; |
412 |
|
debug("%s%s", l_bit? "ldm" : "stm", condition); |
413 |
|
switch (u_bit * 2 + p_bit) { |
414 |
|
case 0: debug("da"); break; |
415 |
|
case 1: debug("db"); break; |
416 |
|
case 2: debug("ia"); break; |
417 |
|
case 3: debug("ib"); break; |
418 |
|
} |
419 |
|
debug("\t%s", arm_regname[r16]); |
420 |
|
if (w_bit) |
421 |
|
debug("!"); |
422 |
|
debug(",{"); |
423 |
|
n = 0; |
424 |
|
for (i=0; i<16; i++) |
425 |
|
if ((iw >> i) & 1) { |
426 |
|
debug("%s%s", (n > 0)? ",":"", arm_regname[i]); |
427 |
|
n++; |
428 |
|
} |
429 |
|
debug("}"); |
430 |
|
if (s_bit) |
431 |
|
debug("^"); |
432 |
|
debug("\n"); |
433 |
break; |
break; |
434 |
case 0xa: /* B: branch */ |
case 0xa: /* B: branch */ |
435 |
case 0xb: /* BL: branch and link */ |
case 0xb: /* BL: branch and link */ |
487 |
} |
} |
488 |
|
|
489 |
|
|
490 |
/* |
#include "tmp_arm_tail.c" |
|
* arm_create_or_reset_tc(): |
|
|
* |
|
|
* Create the translation cache in memory (ie allocate memory for it), if |
|
|
* necessary, and then reset it to an initial state. |
|
|
*/ |
|
|
static void arm_create_or_reset_tc(struct cpu *cpu) |
|
|
{ |
|
|
if (cpu->cd.arm.translation_cache == NULL) { |
|
|
cpu->cd.arm.translation_cache = malloc( |
|
|
ARM_TRANSLATION_CACHE_SIZE + ARM_TRANSLATION_CACHE_MARGIN); |
|
|
if (cpu->cd.arm.translation_cache == NULL) { |
|
|
fprintf(stderr, "arm_create_or_reset_tc(): out of " |
|
|
"memory when allocating the translation cache\n"); |
|
|
exit(1); |
|
|
} |
|
|
} |
|
|
|
|
|
/* Create an empty table at the beginning of the translation cache: */ |
|
|
memset(cpu->cd.arm.translation_cache, 0, sizeof(uint32_t) * |
|
|
N_BASE_TABLE_ENTRIES); |
|
|
|
|
|
cpu->cd.arm.translation_cache_cur_ofs = |
|
|
N_BASE_TABLE_ENTRIES * sizeof(uint32_t); |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* arm_tc_allocate_default_page(): |
|
|
* |
|
|
* Create a default page (with just pointers to instr(to_be_translated) |
|
|
* at cpu->cd.arm.translation_cache_cur_ofs. |
|
|
*/ |
|
|
/* forward declaration of to_be_translated and end_of_page: */ |
|
|
static void instr(to_be_translated)(struct cpu *,struct arm_instr_call *); |
|
|
static void instr(end_of_page)(struct cpu *,struct arm_instr_call *); |
|
|
static void arm_tc_allocate_default_page(struct cpu *cpu, uint32_t physaddr) |
|
|
{ |
|
|
struct arm_tc_physpage *ppp; |
|
|
int i; |
|
|
|
|
|
/* Create the physpage header: */ |
|
|
ppp = (struct arm_tc_physpage *)(cpu->cd.arm.translation_cache |
|
|
+ cpu->cd.arm.translation_cache_cur_ofs); |
|
|
ppp->next_ofs = 0; |
|
|
ppp->physaddr = physaddr; |
|
|
|
|
|
for (i=0; i<IC_ENTRIES_PER_PAGE; i++) |
|
|
ppp->ics[i].f = instr(to_be_translated); |
|
|
|
|
|
ppp->ics[IC_ENTRIES_PER_PAGE].f = instr(end_of_page); |
|
|
|
|
|
cpu->cd.arm.translation_cache_cur_ofs += |
|
|
sizeof(struct arm_tc_physpage); |
|
|
} |
|
|
|
|
|
|
|
|
#define MEMORY_RW arm_memory_rw |
|
|
#define MEM_ARM |
|
|
#include "memory_rw.c" |
|
|
#undef MEM_ARM |
|
|
#undef MEMORY_RW |
|
|
|
|
|
|
|
|
#include "cpu_arm_instr.c" |
|
|
|
|
|
|
|
|
/* |
|
|
* arm_cpu_run_instr(): |
|
|
* |
|
|
* Execute one or more instructions on a specific CPU. |
|
|
* |
|
|
* Return value is the number of instructions executed during this call, |
|
|
* 0 if no instructions were executed. |
|
|
*/ |
|
|
int arm_cpu_run_instr(struct emul *emul, struct cpu *cpu) |
|
|
{ |
|
|
/* |
|
|
* Find the correct translated page in the translation cache, |
|
|
* and start running code on that page. |
|
|
*/ |
|
|
|
|
|
uint32_t cached_pc, physaddr, physpage_ofs; |
|
|
int pagenr, table_index, n_instrs, low_pc; |
|
|
uint32_t *physpage_entryp; |
|
|
struct arm_tc_physpage *ppp; |
|
|
|
|
|
if (cpu->cd.arm.translation_cache == NULL || cpu->cd. |
|
|
arm.translation_cache_cur_ofs >= ARM_TRANSLATION_CACHE_SIZE) |
|
|
arm_create_or_reset_tc(cpu); |
|
|
|
|
|
cached_pc = cpu->cd.arm.r[ARM_PC]; |
|
|
|
|
|
physaddr = cached_pc & ~(((IC_ENTRIES_PER_PAGE-1) << 2) | 3); |
|
|
/* TODO: virtual to physical */ |
|
|
|
|
|
pagenr = ADDR_TO_PAGENR(physaddr); |
|
|
table_index = PAGENR_TO_TABLE_INDEX(pagenr); |
|
|
|
|
|
physpage_entryp = &(((uint32_t *) |
|
|
cpu->cd.arm.translation_cache)[table_index]); |
|
|
physpage_ofs = *physpage_entryp; |
|
|
ppp = NULL; |
|
|
|
|
|
/* Traverse the physical page chain: */ |
|
|
while (physpage_ofs != 0) { |
|
|
ppp = (struct arm_tc_physpage *)(cpu->cd.arm.translation_cache |
|
|
+ physpage_ofs); |
|
|
/* If we found the page in the cache, then we're done: */ |
|
|
if (ppp->physaddr == physaddr) |
|
|
break; |
|
|
/* Try the next page in the chain: */ |
|
|
physpage_ofs = ppp->next_ofs; |
|
|
} |
|
|
|
|
|
/* If the offset is 0 (or ppp is NULL), then we need to create a |
|
|
new "default" empty translation page. */ |
|
|
|
|
|
if (ppp == NULL) { |
|
|
fatal("CREATING page %i (physaddr 0x%08x), table index = %i\n", |
|
|
pagenr, physaddr, table_index); |
|
|
*physpage_entryp = physpage_ofs = |
|
|
cpu->cd.arm.translation_cache_cur_ofs; |
|
|
|
|
|
arm_tc_allocate_default_page(cpu, physaddr); |
|
|
|
|
|
ppp = (struct arm_tc_physpage *)(cpu->cd.arm.translation_cache |
|
|
+ physpage_ofs); |
|
|
} |
|
|
|
|
|
cpu->cd.arm.cur_physpage = ppp; |
|
|
cpu->cd.arm.cur_ic_page = &ppp->ics[0]; |
|
|
cpu->cd.arm.next_ic = cpu->cd.arm.cur_ic_page + |
|
|
PC_TO_IC_ENTRY(cached_pc); |
|
|
|
|
|
/* printf("cached_pc = 0x%08x pagenr = %i table_index = %i, " |
|
|
"physpage_ofs = 0x%08x\n", (int)cached_pc, (int)pagenr, |
|
|
(int)table_index, (int)physpage_ofs); */ |
|
|
|
|
|
cpu->cd.arm.n_translated_instrs = 0; |
|
|
cpu->cd.arm.running_translated = 1; |
|
|
|
|
|
if (single_step || cpu->machine->instruction_trace) { |
|
|
/* |
|
|
* Single-step: |
|
|
*/ |
|
|
struct arm_instr_call *ic = cpu->cd.arm.next_ic ++; |
|
|
if (cpu->machine->instruction_trace) { |
|
|
unsigned char instr[4]; |
|
|
if (!cpu->memory_rw(cpu, cpu->mem, cpu->pc, &instr[0], |
|
|
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
|
|
fatal("arm_cpu_run_instr(): could not read " |
|
|
"the instruction\n"); |
|
|
} else |
|
|
arm_cpu_disassemble_instr(cpu, instr, 1, 0, 0); |
|
|
} |
|
|
|
|
|
/* When single-stepping, multiple instruction calls cannot |
|
|
be combined into one. This clears all translations: */ |
|
|
if (ppp->flags & ARM_COMBINATIONS) { |
|
|
int i; |
|
|
for (i=0; i<IC_ENTRIES_PER_PAGE; i++) |
|
|
ppp->ics[i].f = instr(to_be_translated); |
|
|
debug("[ Note: The translation of physical page 0x%08x" |
|
|
" contained combinations of instructions; these " |
|
|
"are now flushed because we are single-stepping." |
|
|
" ]\n", ppp->physaddr); |
|
|
ppp->flags &= ~ARM_COMBINATIONS; |
|
|
} |
|
|
|
|
|
/* Execute just one instruction: */ |
|
|
ic->f(cpu, ic); |
|
|
n_instrs = 1; |
|
|
} else { |
|
|
/* Execute multiple instructions: */ |
|
|
n_instrs = 0; |
|
|
for (;;) { |
|
|
struct arm_instr_call *ic; |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
|
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
|
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
ic = cpu->cd.arm.next_ic ++; ic->f(cpu, ic); |
|
|
|
|
|
n_instrs += 24; |
|
|
if (!cpu->cd.arm.running_translated || single_step || |
|
|
n_instrs + cpu->cd.arm.n_translated_instrs >= 8192) |
|
|
break; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* Update the program counter and return the correct number of |
|
|
* executed instructions: |
|
|
*/ |
|
|
low_pc = ((size_t)cpu->cd.arm.next_ic - (size_t) |
|
|
cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call); |
|
|
|
|
|
if (low_pc >= 0 && low_pc < IC_ENTRIES_PER_PAGE) { |
|
|
cpu->cd.arm.r[ARM_PC] &= ~((IC_ENTRIES_PER_PAGE-1) << 2); |
|
|
cpu->cd.arm.r[ARM_PC] += (low_pc << 2); |
|
|
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
|
|
} else { |
|
|
fatal("Outside a page (This is actually ok)\n"); |
|
|
} |
|
|
|
|
|
return n_instrs + cpu->cd.arm.n_translated_instrs; |
|
|
} |
|
|
|
|
|
|
|
|
#define CPU_RUN arm_cpu_run |
|
|
#define CPU_RINSTR arm_cpu_run_instr |
|
|
#define CPU_RUN_ARM |
|
|
#include "cpu_run.c" |
|
|
#undef CPU_RINSTR |
|
|
#undef CPU_RUN_ARM |
|
|
#undef CPU_RUN |
|
491 |
|
|
492 |
|
|
|
/* |
|
|
* arm_cpu_family_init(): |
|
|
* |
|
|
* This function fills the cpu_family struct with valid data. |
|
|
*/ |
|
|
int arm_cpu_family_init(struct cpu_family *fp) |
|
|
{ |
|
|
fp->name = "ARM"; |
|
|
fp->cpu_new = arm_cpu_new; |
|
|
fp->list_available_types = arm_cpu_list_available_types; |
|
|
fp->register_match = arm_cpu_register_match; |
|
|
fp->disassemble_instr = arm_cpu_disassemble_instr; |
|
|
fp->register_dump = arm_cpu_register_dump; |
|
|
fp->run = arm_cpu_run; |
|
|
fp->dumpinfo = arm_cpu_dumpinfo; |
|
|
/* fp->show_full_statistics = arm_cpu_show_full_statistics; */ |
|
|
/* fp->tlbdump = arm_cpu_tlbdump; */ |
|
|
/* fp->interrupt = arm_cpu_interrupt; */ |
|
|
/* fp->interrupt_ack = arm_cpu_interrupt_ack; */ |
|
|
return 1; |
|
|
} |
|
|
|
|
493 |
#endif /* ENABLE_ARM */ |
#endif /* ENABLE_ARM */ |