/[gxemul]/trunk/src/cpu_alpha_instr_alu.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/cpu_alpha_instr_alu.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 6140 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_alpha_instr_alu.c,v 1.12 2005/08/07 08:57:54 debug Exp $
29 *
30 * Alpha ALU instructions. (Included from tmp_alpha_misc.c.)
31 *
32 *
33 * Most ALU instructions have the following arguments:
34 *
35 * arg[0] = pointer to destination uint64_t
36 * arg[1] = pointer to source uint64_t nr 1
37 * arg[2] = pointer to source uint64_t nr 2
38 *
39 * or, if ALU_IMM is set, arg[2] contains an 8-bit immediate value.
40 *
41 * The main function groups are:
42 *
43 * ALU_INS inserts
44 * ALU_EXT extracts
45 * ALU_MSK masks
46 * ALU_CMOV conditional moves
47 * ALU_CMP compares
48 * none of the above everything else (add, sub, ...)
49 */
50
51 void ALU_N(struct cpu *cpu, struct alpha_instr_call *ic)
52 {
53 #ifdef ALU_INS
54
55 uint64_t x = *((uint64_t *)ic->arg[1]);
56 int r = (
57 #ifdef ALU_IMM
58 ic->arg[2]
59 #else
60 (*((uint64_t *)ic->arg[2]))
61 #endif
62 & 7) * 8;
63
64 #ifdef ALU_B
65 x &= 0xff;
66 #endif
67 #ifdef ALU_W
68 x &= 0xffff;
69 #endif
70 #ifdef ALU_L
71 x &= 0xffffffffULL;
72 #endif
73
74 #ifdef ALU_LO
75 x <<= r;
76 #else
77 r = 64 - r;
78 if (r == 64)
79 x = 0;
80 else
81 x >>= r;
82 #endif
83 *((uint64_t *)ic->arg[0]) = x;
84
85 #else /* ! INS */
86
87 #ifdef ALU_EXT
88
89 uint64_t x = *((uint64_t *)ic->arg[1]);
90 int r = (
91 #ifdef ALU_IMM
92 ic->arg[2]
93 #else
94 (*((uint64_t *)ic->arg[2]))
95 #endif
96 & 7) * 8;
97 #ifdef ALU_LO
98 x >>= r;
99 #else
100 r = 64 - r;
101 if (r != 64)
102 x <<= r;
103 #endif
104 #ifdef ALU_B
105 x &= 0xff;
106 #endif
107 #ifdef ALU_W
108 x &= 0xffff;
109 #endif
110 #ifdef ALU_L
111 x &= 0xffffffffULL;
112 #endif
113 *((uint64_t *)ic->arg[0]) = x;
114
115 #else /* ! EXT */
116
117 #ifdef ALU_MSK
118
119 uint64_t x = *((uint64_t *)ic->arg[1]);
120 #ifdef ALU_B
121 uint64_t mask = 0x00000000000000ffULL;
122 #endif
123 #ifdef ALU_W
124 uint64_t mask = 0x000000000000ffffULL;
125 #endif
126 #ifdef ALU_L
127 uint64_t mask = 0x00000000ffffffffULL;
128 #endif
129 #ifdef ALU_Q
130 uint64_t mask = 0xffffffffffffffffULL;
131 #endif
132 int r = (
133 #ifdef ALU_IMM
134 ic->arg[2]
135 #else
136 (*((uint64_t *)ic->arg[2]))
137 #endif
138 & 7) * 8;
139
140 #ifdef ALU_LO
141 mask <<= r;
142 #else
143 if (r == 0)
144 mask = 0;
145 else
146 mask >>= (64 - r);
147 #endif
148
149 *((uint64_t *)ic->arg[0]) = x & ~mask;
150
151 #else /* !MSK */
152
153 #ifdef ALU_CMOV
154
155 if (
156 #ifdef ALU_CMOV_lbc
157 !(
158 #endif
159 (*((int64_t *)ic->arg[1]))
160 #ifdef ALU_CMOV_eq
161 == 0
162 #endif
163 #ifdef ALU_CMOV_ne
164 != 0
165 #endif
166 #ifdef ALU_CMOV_le
167 <= 0
168 #endif
169 #ifdef ALU_CMOV_lt
170 < 0
171 #endif
172 #ifdef ALU_CMOV_ge
173 >= 0
174 #endif
175 #ifdef ALU_CMOV_gt
176 > 0
177 #endif
178 #ifdef ALU_CMOV_lbs
179 & 1
180 #endif
181 #ifdef ALU_CMOV_lbc
182 & 1)
183 #endif
184 )
185 *((uint64_t *)ic->arg[0]) =
186 #ifdef ALU_IMM
187 (uint64_t)ic->arg[2]
188 #else
189 (*((uint64_t *)ic->arg[2]))
190 #endif
191 ;
192
193 #else /* ! CMOV */
194
195 #ifdef ALU_CMP
196
197 uint64_t x;
198
199 x = (*((
200 #ifdef ALU_UNSIGNED
201 uint64_t
202 #else
203 int64_t
204 #endif
205 *)ic->arg[1]))
206
207 #ifdef ALU_CMP_EQ
208 ==
209 #endif
210 #ifdef ALU_CMP_LE
211 <=
212 #endif
213 #ifdef ALU_CMP_LT
214 <
215 #endif
216
217 #ifdef ALU_IMM
218 #ifdef ALU_UNSIGNED
219 (uint64_t)ic->arg[2]
220 #else
221 (int64_t)ic->arg[2]
222 #endif
223 #else
224 #ifdef ALU_UNSIGNED
225 (*((uint64_t *)ic->arg[2]))
226 #else
227 (*((int64_t *)ic->arg[2]))
228 #endif
229 #endif
230 ;
231
232 #else /* !ALU_CMP */
233
234 #ifdef ALU_LONG
235 /* Long */
236 int32_t x;
237 #else
238 /* Quad */
239 int64_t x;
240 #endif
241
242 #ifdef ALU_ZAP
243 /* Prepare for zapping: */
244 uint64_t zapmask = 0xffffffffffffffffULL;
245 int zapbytes =
246 #ifdef ALU_NOT
247 ~
248 #endif
249 #ifdef ALU_IMM
250 (int64_t)ic->arg[2]
251 #else
252 (*((uint64_t *)ic->arg[2]))
253 #endif
254 ;
255 if (zapbytes & 0x80)
256 zapmask &= ~0xff00000000000000ULL;
257 if (zapbytes & 0x40)
258 zapmask &= ~0xff000000000000ULL;
259 if (zapbytes & 0x20)
260 zapmask &= ~0xff0000000000ULL;
261 if (zapbytes & 0x10)
262 zapmask &= ~0xff00000000ULL;
263 if (zapbytes & 0x08)
264 zapmask &= ~0xff000000ULL;
265 if (zapbytes & 0x04)
266 zapmask &= ~0xff0000ULL;
267 if (zapbytes & 0x02)
268 zapmask &= ~0xff00ULL;
269 if (zapbytes & 0x01)
270 zapmask &= ~0xffULL;
271 #endif /* ZAP */
272
273 x = (
274 #ifdef ALU_SRA
275 (int64_t)
276 #endif
277 (*((uint64_t *)ic->arg[1]))
278 #ifdef ALU_S4
279 * 4
280 #endif
281 #ifdef ALU_S8
282 * 8
283 #endif
284 )
285 #ifdef ALU_ADD
286 +
287 #endif
288 #ifdef ALU_SUB
289 -
290 #endif
291 #ifdef ALU_OR
292 |
293 #endif
294 #ifdef ALU_XOR
295 ^
296 #endif
297 #ifdef ALU_AND
298 &
299 #endif
300 #ifdef ALU_SLL
301 <<
302 #endif
303 #if defined(ALU_SRA) || defined(ALU_SRL)
304 >>
305 #endif
306
307 #ifdef ALU_ZAP
308 & zapmask
309 #else /* !ZAP */
310 (
311 #ifdef ALU_NOT
312 ~
313 #endif
314 (
315 #ifdef ALU_IMM
316 (int64_t)ic->arg[2]
317 #else
318 (*((uint64_t *)ic->arg[2]))
319 #endif
320 #if defined(ALU_SRA) || defined(ALU_SRL) || defined(ALU_SLL)
321 & 63
322 #endif
323 )
324 )
325 #endif /* !ZAP */
326
327 ;
328
329 #endif /* !ALU_CMP */
330
331 *((uint64_t *)ic->arg[0]) = x;
332 #endif /* ! CMOV */
333 #endif /* ! MSK */
334 #endif /* ! EXT */
335 #endif /* ! INS */
336 }
337

  ViewVC Help
Powered by ViewVC 1.1.26