/[gxemul]/trunk/src/cpu.c
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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 16096 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============
1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu.c,v 1.361 2006/10/25 09:24:05 debug Exp $
29 *
30 * Common routines for CPU emulation. (Not specific to any CPU type.)
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <sys/types.h>
36 #include <sys/mman.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43 #include "settings.h"
44
45
46 static struct cpu_family *first_cpu_family = NULL;
47
48
49 /*
50 * cpu_new():
51 *
52 * Create a new cpu object. Each family is tried in sequence until a
53 * CPU family recognizes the cpu_type_name.
54 *
55 * If there was no match, NULL is returned. Otherwise, a pointer to an
56 * initialized cpu struct is returned.
57 */
58 struct cpu *cpu_new(struct memory *mem, struct machine *machine,
59 int cpu_id, char *name)
60 {
61 struct cpu *cpu;
62 struct cpu_family *fp;
63 char *cpu_type_name;
64 char tmpstr[30];
65
66 if (name == NULL) {
67 fprintf(stderr, "cpu_new(): cpu name = NULL?\n");
68 exit(1);
69 }
70
71 cpu_type_name = strdup(name);
72 if (cpu_type_name == NULL) {
73 fprintf(stderr, "cpu_new(): out of memory\n");
74 exit(1);
75 }
76
77 cpu = zeroed_alloc(sizeof(struct cpu));
78
79 cpu->memory_rw = NULL;
80 cpu->name = cpu_type_name;
81 cpu->mem = mem;
82 cpu->machine = machine;
83 cpu->cpu_id = cpu_id;
84 cpu->byte_order = EMUL_UNDEFINED_ENDIAN;
85 cpu->running = 0;
86
87 /* Create settings, and attach to the machine: */
88 cpu->settings = settings_new();
89 snprintf(tmpstr, sizeof(tmpstr), "cpu[%i]", cpu_id);
90 settings_add(machine->settings, tmpstr, 1,
91 SETTINGS_TYPE_SUBSETTINGS, 0, cpu->settings);
92
93 settings_add(cpu->settings, "name", 0, SETTINGS_TYPE_STRING,
94 SETTINGS_FORMAT_STRING, (void *) &cpu->name);
95 settings_add(cpu->settings, "running", 0, SETTINGS_TYPE_INT,
96 SETTINGS_FORMAT_YESNO, (void *) &cpu->running);
97
98 cpu_create_or_reset_tc(cpu);
99
100 fp = first_cpu_family;
101
102 while (fp != NULL) {
103 if (fp->cpu_new != NULL) {
104 if (fp->cpu_new(cpu, mem, machine, cpu_id,
105 cpu_type_name)) {
106 /* Sanity check: */
107 if (cpu->memory_rw == NULL) {
108 fatal("\ncpu_new(): memory_rw == "
109 "NULL\n");
110 exit(1);
111 }
112 break;
113 }
114 }
115
116 fp = fp->next;
117 }
118
119 if (fp == NULL) {
120 fatal("\ncpu_new(): unknown cpu type '%s'\n", cpu_type_name);
121 return NULL;
122 }
123
124 fp->init_tables(cpu);
125
126 if (cpu->byte_order == EMUL_UNDEFINED_ENDIAN) {
127 fatal("\ncpu_new(): Internal bug: Endianness not set.\n");
128 exit(1);
129 }
130
131 return cpu;
132 }
133
134
135 /*
136 * cpu_destroy():
137 *
138 * Destroy a cpu object.
139 */
140 void cpu_destroy(struct cpu *cpu)
141 {
142 settings_remove(cpu->settings, "name");
143 settings_remove(cpu->settings, "running");
144
145 /* Remove any remaining level-1 settings: */
146 settings_remove_all(cpu->settings);
147
148 settings_destroy(cpu->settings);
149
150 /* TODO: This assumes that zeroed_alloc() actually succeeded
151 with using mmap(), and not malloc()! */
152 munmap((void *)cpu, sizeof(struct cpu));
153 }
154
155
156 /*
157 * cpu_tlbdump():
158 *
159 * Called from the debugger to dump the TLB in a readable format.
160 * x is the cpu number to dump, or -1 to dump all CPUs.
161 *
162 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
163 * just dumped.
164 */
165 void cpu_tlbdump(struct machine *m, int x, int rawflag)
166 {
167 if (m->cpu_family == NULL || m->cpu_family->tlbdump == NULL)
168 fatal("cpu_tlbdump(): NULL\n");
169 else
170 m->cpu_family->tlbdump(m, x, rawflag);
171 }
172
173
174 /*
175 * cpu_disassemble_instr():
176 *
177 * Convert an instruction word into human readable format, for instruction
178 * tracing.
179 */
180 int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
181 unsigned char *instr, int running, uint64_t addr)
182 {
183 if (m->cpu_family == NULL || m->cpu_family->disassemble_instr == NULL) {
184 fatal("cpu_disassemble_instr(): NULL\n");
185 return 0;
186 } else
187 return m->cpu_family->disassemble_instr(cpu, instr,
188 running, addr);
189 }
190
191
192 /*
193 * cpu_register_dump():
194 *
195 * Dump cpu registers in a relatively readable format.
196 *
197 * gprs: set to non-zero to dump GPRs. (CPU dependent.)
198 * coprocs: set bit 0..x to dump registers in coproc 0..x. (CPU dependent.)
199 */
200 void cpu_register_dump(struct machine *m, struct cpu *cpu,
201 int gprs, int coprocs)
202 {
203 if (m->cpu_family == NULL || m->cpu_family->register_dump == NULL)
204 fatal("cpu_register_dump(): NULL\n");
205 else
206 m->cpu_family->register_dump(cpu, gprs, coprocs);
207 }
208
209
210 /*
211 * cpu_gdb_stub():
212 *
213 * Execute a "remote GDB" command. Return value is a pointer to a newly
214 * allocated response string, if the command was successfully executed. If
215 * there was an error, NULL is returned.
216 */
217 char *cpu_gdb_stub(struct cpu *cpu, char *cmd)
218 {
219 if (cpu->machine->cpu_family == NULL ||
220 cpu->machine->cpu_family->gdb_stub == NULL) {
221 fatal("cpu_gdb_stub(): NULL\n");
222 return NULL;
223 } else
224 return cpu->machine->cpu_family->gdb_stub(cpu, cmd);
225 }
226
227
228 /*
229 * cpu_interrupt():
230 *
231 * Assert an interrupt.
232 * Return value is 1 if the interrupt was asserted, 0 otherwise.
233 */
234 int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
235 {
236 if (cpu->machine->cpu_family == NULL ||
237 cpu->machine->cpu_family->interrupt == NULL) {
238 fatal("cpu_interrupt(): NULL\n");
239 return 0;
240 } else
241 return cpu->machine->cpu_family->interrupt(cpu, irq_nr);
242 }
243
244
245 /*
246 * cpu_interrupt_ack():
247 *
248 * Acknowledge an interrupt.
249 * Return value is 1 if the interrupt was deasserted, 0 otherwise.
250 */
251 int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
252 {
253 if (cpu->machine->cpu_family == NULL ||
254 cpu->machine->cpu_family->interrupt_ack == NULL) {
255 /* debug("cpu_interrupt_ack(): NULL\n"); */
256 return 0;
257 } else
258 return cpu->machine->cpu_family->interrupt_ack(cpu, irq_nr);
259 }
260
261
262 /*
263 * cpu_functioncall_trace():
264 *
265 * This function should be called if machine->show_trace_tree is enabled, and
266 * a function call is being made. f contains the address of the function.
267 */
268 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f)
269 {
270 int i, n_args = -1;
271 char *symbol;
272 uint64_t offset;
273
274 if (cpu->machine->ncpus > 1)
275 fatal("cpu%i:\t", cpu->cpu_id);
276
277 cpu->trace_tree_depth ++;
278 if (cpu->trace_tree_depth > 100)
279 cpu->trace_tree_depth = 100;
280 for (i=0; i<cpu->trace_tree_depth; i++)
281 fatal(" ");
282
283 fatal("<");
284 symbol = get_symbol_name_and_n_args(&cpu->machine->symbol_context,
285 f, &offset, &n_args);
286 if (symbol != NULL)
287 fatal("%s", symbol);
288 else {
289 if (cpu->is_32bit)
290 fatal("0x%"PRIx32, (uint32_t) f);
291 else
292 fatal("0x%"PRIx64, (uint64_t) f);
293 }
294 fatal("(");
295
296 if (cpu->machine->cpu_family->functioncall_trace != NULL)
297 cpu->machine->cpu_family->functioncall_trace(cpu, f, n_args);
298
299 fatal(")>\n");
300
301 #ifdef PRINT_MEMORY_CHECKSUM
302 /* Temporary hack for finding bugs: */
303 fatal("call chksum=%016"PRIx64"\n", memory_checksum(cpu->mem));
304 #endif
305 }
306
307
308 /*
309 * cpu_functioncall_trace_return():
310 *
311 * This function should be called if machine->show_trace_tree is enabled, and
312 * a function is being returned from.
313 *
314 * TODO: Print return value? This could be implemented similar to the
315 * cpu->functioncall_trace function call above.
316 */
317 void cpu_functioncall_trace_return(struct cpu *cpu)
318 {
319 cpu->trace_tree_depth --;
320 if (cpu->trace_tree_depth < 0)
321 cpu->trace_tree_depth = 0;
322 }
323
324
325 /*
326 * cpu_create_or_reset_tc():
327 *
328 * Create the translation cache in memory (ie allocate memory for it), if
329 * necessary, and then reset it to an initial state.
330 */
331 void cpu_create_or_reset_tc(struct cpu *cpu)
332 {
333 size_t s = DYNTRANS_CACHE_SIZE + DYNTRANS_CACHE_MARGIN;
334
335 if (cpu->translation_cache == NULL)
336 cpu->translation_cache = zeroed_alloc(s);
337
338 /* Create an empty table at the beginning of the translation cache: */
339 memset(cpu->translation_cache, 0, sizeof(uint32_t)
340 * N_BASE_TABLE_ENTRIES);
341
342 cpu->translation_cache_cur_ofs =
343 N_BASE_TABLE_ENTRIES * sizeof(uint32_t);
344
345 /*
346 * There might be other translation pointers that still point to
347 * within the translation_cache region. Let's invalidate those too:
348 */
349 if (cpu->invalidate_code_translation != NULL)
350 cpu->invalidate_code_translation(cpu, 0, INVALIDATE_ALL);
351 }
352
353
354 /*
355 * cpu_dumpinfo():
356 *
357 * Dumps info about a CPU using debug(). "cpu0: CPUNAME, running" (or similar)
358 * is outputed, and it is up to CPU dependent code to complete the line.
359 */
360 void cpu_dumpinfo(struct machine *m, struct cpu *cpu)
361 {
362 debug("cpu%i: %s, %s", cpu->cpu_id, cpu->name,
363 cpu->running? "running" : "stopped");
364
365 if (m->cpu_family == NULL || m->cpu_family->dumpinfo == NULL)
366 fatal("cpu_dumpinfo(): NULL\n");
367 else
368 m->cpu_family->dumpinfo(cpu);
369 }
370
371
372 /*
373 * cpu_list_available_types():
374 *
375 * Print a list of available CPU types for each cpu family.
376 */
377 void cpu_list_available_types(void)
378 {
379 struct cpu_family *fp;
380 int iadd = DEBUG_INDENTATION;
381
382 fp = first_cpu_family;
383
384 if (fp == NULL) {
385 debug("No CPUs defined!\n");
386 return;
387 }
388
389 while (fp != NULL) {
390 debug("%s:\n", fp->name);
391 debug_indentation(iadd);
392 if (fp->list_available_types != NULL)
393 fp->list_available_types();
394 else
395 debug("(internal error: list_available_types"
396 " = NULL)\n");
397 debug_indentation(-iadd);
398
399 fp = fp->next;
400 }
401 }
402
403
404 /*
405 * cpu_run_deinit():
406 *
407 * Shuts down all CPUs in a machine when ending a simulation. (This function
408 * should only need to be called once for each machine.)
409 */
410 void cpu_run_deinit(struct machine *machine)
411 {
412 int te;
413
414 /*
415 * Two last ticks of every hardware device. This will allow e.g.
416 * framebuffers to draw the last updates to the screen before halting.
417 *
418 * TODO: This should be refactored when redesigning the mainbus
419 * concepts!
420 */
421 for (te=0; te<machine->n_tick_entries; te++) {
422 machine->tick_func[te](machine->cpus[0],
423 machine->tick_extra[te]);
424 machine->tick_func[te](machine->cpus[0],
425 machine->tick_extra[te]);
426 }
427
428 if (machine->show_nr_of_instructions)
429 cpu_show_cycles(machine, 1);
430
431 fflush(stdout);
432 }
433
434
435 /*
436 * cpu_show_cycles():
437 *
438 * If show_nr_of_instructions is on, then print a line to stdout about how
439 * many instructions/cycles have been executed so far.
440 */
441 void cpu_show_cycles(struct machine *machine, int forced)
442 {
443 uint64_t offset, pc;
444 char *symbol;
445 int64_t mseconds, ninstrs, is, avg;
446 struct timeval tv;
447 struct cpu *cpu = machine->cpus[machine->bootstrap_cpu];
448
449 static int64_t mseconds_last = 0;
450 static int64_t ninstrs_last = -1;
451
452 pc = cpu->pc;
453
454 gettimeofday(&tv, NULL);
455 mseconds = (tv.tv_sec - machine->starttime.tv_sec) * 1000
456 + (tv.tv_usec - machine->starttime.tv_usec) / 1000;
457
458 if (mseconds == 0)
459 mseconds = 1;
460
461 if (mseconds - mseconds_last == 0)
462 mseconds ++;
463
464 ninstrs = machine->ninstrs_since_gettimeofday;
465
466 /* RETURN here, unless show_nr_of_instructions (-N) is turned on: */
467 if (!machine->show_nr_of_instructions && !forced)
468 goto do_return;
469
470 printf("[ %"PRIi64" instrs", (int64_t)machine->ninstrs);
471
472 /* Instructions per second, and average so far: */
473 is = 1000 * (ninstrs-ninstrs_last) / (mseconds-mseconds_last);
474 avg = (long long)1000 * ninstrs / mseconds;
475 if (is < 0)
476 is = 0;
477 if (avg < 0)
478 avg = 0;
479
480 if (cpu->has_been_idling) {
481 printf("; idling");
482 cpu->has_been_idling = 0;
483 } else
484 printf("; i/s=%"PRIi64" avg=%"PRIi64, is, avg);
485
486 symbol = get_symbol_name(&machine->symbol_context, pc, &offset);
487
488 if (machine->ncpus == 1) {
489 if (cpu->is_32bit)
490 printf("; pc=0x%08"PRIx32, (uint32_t) pc);
491 else
492 printf("; pc=0x%016"PRIx64, (uint64_t) pc);
493 }
494
495 if (symbol != NULL)
496 printf(" <%s>", symbol);
497 printf(" ]\n");
498
499 do_return:
500 ninstrs_last = ninstrs;
501 mseconds_last = mseconds;
502 }
503
504
505 /*
506 * cpu_run_init():
507 *
508 * Prepare to run instructions on all CPUs in this machine. (This function
509 * should only need to be called once for each machine.)
510 */
511 void cpu_run_init(struct machine *machine)
512 {
513 machine->ninstrs_flush = 0;
514 machine->ninstrs = 0;
515 machine->ninstrs_show = 0;
516
517 /* For performance measurement: */
518 gettimeofday(&machine->starttime, NULL);
519 machine->ninstrs_since_gettimeofday = 0;
520 }
521
522
523 /*
524 * add_cpu_family():
525 *
526 * Allocates a cpu_family struct and calls an init function for the
527 * family to fill in reasonable data and pointers.
528 */
529 static void add_cpu_family(int (*family_init)(struct cpu_family *), int arch)
530 {
531 struct cpu_family *fp, *tmp;
532 int res;
533
534 fp = malloc(sizeof(struct cpu_family));
535 if (fp == NULL) {
536 fprintf(stderr, "add_cpu_family(): out of memory\n");
537 exit(1);
538 }
539 memset(fp, 0, sizeof(struct cpu_family));
540
541 /*
542 * family_init() returns 1 if the struct has been filled with
543 * valid data, 0 if suppor for the cpu family isn't compiled
544 * into the emulator.
545 */
546 res = family_init(fp);
547 if (!res) {
548 free(fp);
549 return;
550 }
551 fp->arch = arch;
552 fp->next = NULL;
553
554 /* Add last in family chain: */
555 tmp = first_cpu_family;
556 if (tmp == NULL) {
557 first_cpu_family = fp;
558 } else {
559 while (tmp->next != NULL)
560 tmp = tmp->next;
561 tmp->next = fp;
562 }
563 }
564
565
566 /*
567 * cpu_family_ptr_by_number():
568 *
569 * Returns a pointer to a CPU family based on the ARCH_* integers.
570 */
571 struct cpu_family *cpu_family_ptr_by_number(int arch)
572 {
573 struct cpu_family *fp;
574 fp = first_cpu_family;
575
576 /* YUCK! This is too hardcoded! TODO */
577
578 while (fp != NULL) {
579 if (arch == fp->arch)
580 return fp;
581 fp = fp->next;
582 }
583
584 return NULL;
585 }
586
587
588 /*
589 * cpu_init():
590 *
591 * Should be called before any other cpu_*() function.
592 *
593 * TODO: Make this nicer by moving out the conditional stuff to
594 * an automagically generated file? Or a define in config.h?
595 */
596 void cpu_init(void)
597 {
598 /* Note: These are registered in alphabetic order. */
599
600 #ifdef ENABLE_ALPHA
601 add_cpu_family(alpha_cpu_family_init, ARCH_ALPHA);
602 #endif
603
604 #ifdef ENABLE_ARM
605 add_cpu_family(arm_cpu_family_init, ARCH_ARM);
606 #endif
607
608 #ifdef ENABLE_AVR
609 add_cpu_family(avr_cpu_family_init, ARCH_AVR);
610 #endif
611
612 #ifdef ENABLE_AVR32
613 add_cpu_family(avr32_cpu_family_init, ARCH_AVR32);
614 #endif
615
616 #ifdef ENABLE_RCA180X
617 add_cpu_family(rca180x_cpu_family_init, ARCH_RCA180X);
618 #endif
619
620 #ifdef ENABLE_HPPA
621 add_cpu_family(hppa_cpu_family_init, ARCH_HPPA);
622 #endif
623
624 #ifdef ENABLE_I960
625 add_cpu_family(i960_cpu_family_init, ARCH_I960);
626 #endif
627
628 #ifdef ENABLE_IA64
629 add_cpu_family(ia64_cpu_family_init, ARCH_IA64);
630 #endif
631
632 #ifdef ENABLE_M68K
633 add_cpu_family(m68k_cpu_family_init, ARCH_M68K);
634 #endif
635
636 #ifdef ENABLE_MIPS
637 add_cpu_family(mips_cpu_family_init, ARCH_MIPS);
638 #endif
639
640 #ifdef ENABLE_PPC
641 add_cpu_family(ppc_cpu_family_init, ARCH_PPC);
642 #endif
643
644 #ifdef ENABLE_SH
645 add_cpu_family(sh_cpu_family_init, ARCH_SH);
646 #endif
647
648 #ifdef ENABLE_SPARC
649 add_cpu_family(sparc_cpu_family_init, ARCH_SPARC);
650 #endif
651
652 #ifdef ENABLE_TRANSPUTER
653 add_cpu_family(transputer_cpu_family_init, ARCH_TRANSPUTER);
654 #endif
655
656 #ifdef ENABLE_X86
657 add_cpu_family(x86_cpu_family_init, ARCH_X86);
658 #endif
659 }
660
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