/[gxemul]/trunk/src/cpu.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/cpu.c

Parent Directory Parent Directory | Revision Log Revision Log

Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 17059 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============
1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu.c,v 1.342 2006/06/22 13:27:03 debug Exp $
29 *
30 * Common routines for CPU emulation. (Not specific to any CPU type.)
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <sys/types.h>
36 #include <sys/mman.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43
44
45 extern int quiet_mode;
46
47 static struct cpu_family *first_cpu_family = NULL;
48
49
50 /*
51 * cpu_new():
52 *
53 * Create a new cpu object. Each family is tried in sequence until a
54 * CPU family recognizes the cpu_type_name.
55 */
56 struct cpu *cpu_new(struct memory *mem, struct machine *machine,
57 int cpu_id, char *name)
58 {
59 struct cpu *cpu;
60 struct cpu_family *fp;
61 char *cpu_type_name;
62
63 if (name == NULL) {
64 fprintf(stderr, "cpu_new(): cpu name = NULL?\n");
65 exit(1);
66 }
67
68 cpu_type_name = strdup(name);
69 if (cpu_type_name == NULL) {
70 fprintf(stderr, "cpu_new(): out of memory\n");
71 exit(1);
72 }
73
74 cpu = zeroed_alloc(sizeof(struct cpu));
75
76 cpu->memory_rw = NULL;
77 cpu->name = cpu_type_name;
78 cpu->mem = mem;
79 cpu->machine = machine;
80 cpu->cpu_id = cpu_id;
81 cpu->byte_order = EMUL_LITTLE_ENDIAN;
82 cpu->bootstrap_cpu_flag = 0;
83 cpu->running = 0;
84
85 cpu_create_or_reset_tc(cpu);
86
87 fp = first_cpu_family;
88
89 while (fp != NULL) {
90 if (fp->cpu_new != NULL) {
91 if (fp->cpu_new(cpu, mem, machine, cpu_id,
92 cpu_type_name)) {
93 /* Sanity check: */
94 if (cpu->memory_rw == NULL) {
95 fatal("\ncpu_new(): memory_rw == "
96 "NULL\n");
97 exit(1);
98 }
99 return cpu;
100 }
101 }
102
103 fp = fp->next;
104 }
105
106 fatal("\ncpu_new(): unknown cpu type '%s'\n", cpu_type_name);
107 return NULL;
108 }
109
110
111 /*
112 * cpu_tlbdump():
113 *
114 * Called from the debugger to dump the TLB in a readable format.
115 * x is the cpu number to dump, or -1 to dump all CPUs.
116 *
117 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
118 * just dumped.
119 */
120 void cpu_tlbdump(struct machine *m, int x, int rawflag)
121 {
122 if (m->cpu_family == NULL || m->cpu_family->tlbdump == NULL)
123 fatal("cpu_tlbdump(): NULL\n");
124 else
125 m->cpu_family->tlbdump(m, x, rawflag);
126 }
127
128
129 /*
130 * cpu_register_match():
131 *
132 * Used by the debugger.
133 */
134 void cpu_register_match(struct machine *m, char *name,
135 int writeflag, uint64_t *valuep, int *match_register)
136 {
137 if (m->cpu_family == NULL || m->cpu_family->register_match == NULL)
138 fatal("cpu_register_match(): NULL\n");
139 else
140 m->cpu_family->register_match(m, name, writeflag,
141 valuep, match_register);
142 }
143
144
145 /*
146 * cpu_disassemble_instr():
147 *
148 * Convert an instruction word into human readable format, for instruction
149 * tracing.
150 */
151 int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
152 unsigned char *instr, int running, uint64_t addr)
153 {
154 if (m->cpu_family == NULL || m->cpu_family->disassemble_instr == NULL) {
155 fatal("cpu_disassemble_instr(): NULL\n");
156 return 0;
157 } else
158 return m->cpu_family->disassemble_instr(cpu, instr,
159 running, addr);
160 }
161
162
163 /*
164 * cpu_register_dump():
165 *
166 * Dump cpu registers in a relatively readable format.
167 *
168 * gprs: set to non-zero to dump GPRs. (CPU dependent.)
169 * coprocs: set bit 0..x to dump registers in coproc 0..x. (CPU dependent.)
170 */
171 void cpu_register_dump(struct machine *m, struct cpu *cpu,
172 int gprs, int coprocs)
173 {
174 if (m->cpu_family == NULL || m->cpu_family->register_dump == NULL)
175 fatal("cpu_register_dump(): NULL\n");
176 else
177 m->cpu_family->register_dump(cpu, gprs, coprocs);
178 }
179
180
181 /*
182 * cpu_gdb_stub():
183 *
184 * Execute a "remote GDB" command. Return value is a pointer to a newly
185 * allocated response string, if the command was successfully executed. If
186 * there was an error, NULL is returned.
187 */
188 char *cpu_gdb_stub(struct cpu *cpu, char *cmd)
189 {
190 if (cpu->machine->cpu_family == NULL ||
191 cpu->machine->cpu_family->gdb_stub == NULL) {
192 fatal("cpu_gdb_stub(): NULL\n");
193 return NULL;
194 } else
195 return cpu->machine->cpu_family->gdb_stub(cpu, cmd);
196 }
197
198
199 /*
200 * cpu_interrupt():
201 *
202 * Assert an interrupt.
203 * Return value is 1 if the interrupt was asserted, 0 otherwise.
204 */
205 int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
206 {
207 if (cpu->machine->cpu_family == NULL ||
208 cpu->machine->cpu_family->interrupt == NULL) {
209 fatal("cpu_interrupt(): NULL\n");
210 return 0;
211 } else
212 return cpu->machine->cpu_family->interrupt(cpu, irq_nr);
213 }
214
215
216 /*
217 * cpu_interrupt_ack():
218 *
219 * Acknowledge an interrupt.
220 * Return value is 1 if the interrupt was deasserted, 0 otherwise.
221 */
222 int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
223 {
224 if (cpu->machine->cpu_family == NULL ||
225 cpu->machine->cpu_family->interrupt_ack == NULL) {
226 /* debug("cpu_interrupt_ack(): NULL\n"); */
227 return 0;
228 } else
229 return cpu->machine->cpu_family->interrupt_ack(cpu, irq_nr);
230 }
231
232
233 /*
234 * cpu_functioncall_trace():
235 *
236 * This function should be called if machine->show_trace_tree is enabled, and
237 * a function call is being made. f contains the address of the function.
238 */
239 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f)
240 {
241 int i, n_args = -1;
242 char *symbol;
243 uint64_t offset;
244
245 if (cpu->machine->ncpus > 1)
246 fatal("cpu%i:\t", cpu->cpu_id);
247
248 cpu->trace_tree_depth ++;
249 if (cpu->trace_tree_depth > 100)
250 cpu->trace_tree_depth = 100;
251 for (i=0; i<cpu->trace_tree_depth; i++)
252 fatal(" ");
253
254 fatal("<");
255 symbol = get_symbol_name_and_n_args(&cpu->machine->symbol_context,
256 f, &offset, &n_args);
257 if (symbol != NULL)
258 fatal("%s", symbol);
259 else {
260 if (cpu->is_32bit)
261 fatal("0x%"PRIx32, (uint32_t) f);
262 else
263 fatal("0x%"PRIx64, (uint64_t) f);
264 }
265 fatal("(");
266
267 if (cpu->machine->cpu_family->functioncall_trace != NULL)
268 cpu->machine->cpu_family->functioncall_trace(cpu, f, n_args);
269
270 fatal(")>\n");
271
272 #ifdef PRINT_MEMORY_CHECKSUM
273 /* Temporary hack for finding bugs: */
274 fatal("call chksum=%016"PRIx64"\n", memory_checksum(cpu->mem));
275 #endif
276 }
277
278
279 /*
280 * cpu_functioncall_trace_return():
281 *
282 * This function should be called if machine->show_trace_tree is enabled, and
283 * a function is being returned from.
284 *
285 * TODO: Print return value? This could be implemented similar to the
286 * cpu->functioncall_trace function call above.
287 */
288 void cpu_functioncall_trace_return(struct cpu *cpu)
289 {
290 cpu->trace_tree_depth --;
291 if (cpu->trace_tree_depth < 0)
292 cpu->trace_tree_depth = 0;
293 }
294
295
296 /*
297 * cpu_create_or_reset_tc():
298 *
299 * Create the translation cache in memory (ie allocate memory for it), if
300 * necessary, and then reset it to an initial state.
301 */
302 void cpu_create_or_reset_tc(struct cpu *cpu)
303 {
304 size_t s = DYNTRANS_CACHE_SIZE + DYNTRANS_CACHE_MARGIN;
305
306 if (cpu->translation_cache == NULL)
307 cpu->translation_cache = zeroed_alloc(s);
308
309 /* Create an empty table at the beginning of the translation cache: */
310 memset(cpu->translation_cache, 0, sizeof(uint32_t)
311 * N_BASE_TABLE_ENTRIES);
312
313 cpu->translation_cache_cur_ofs =
314 N_BASE_TABLE_ENTRIES * sizeof(uint32_t);
315
316 /*
317 * There might be other translation pointers that still point to
318 * within the translation_cache region. Let's invalidate those too:
319 */
320 if (cpu->invalidate_code_translation != NULL)
321 cpu->invalidate_code_translation(cpu, 0, INVALIDATE_ALL);
322 }
323
324
325 /*
326 * cpu_run():
327 *
328 * Run instructions on all CPUs in this machine, for a "medium duration"
329 * (or until all CPUs have halted).
330 *
331 * Return value is 1 if anything happened, 0 if all CPUs are stopped.
332 */
333 int cpu_run(struct emul *emul, struct machine *m)
334 {
335 if (m->cpu_family == NULL || m->cpu_family->run == NULL) {
336 fatal("cpu_run(): NULL\n");
337 return 0;
338 } else
339 return m->cpu_family->run(emul, m);
340 }
341
342
343 /*
344 * cpu_dumpinfo():
345 *
346 * Dumps info about a CPU using debug(). "cpu0: CPUNAME, running" (or similar)
347 * is outputed, and it is up to CPU dependent code to complete the line.
348 */
349 void cpu_dumpinfo(struct machine *m, struct cpu *cpu)
350 {
351 debug("cpu%i: %s, %s", cpu->cpu_id, cpu->name,
352 cpu->running? "running" : "stopped");
353
354 if (m->cpu_family == NULL || m->cpu_family->dumpinfo == NULL)
355 fatal("cpu_dumpinfo(): NULL\n");
356 else
357 m->cpu_family->dumpinfo(cpu);
358 }
359
360
361 /*
362 * cpu_list_available_types():
363 *
364 * Print a list of available CPU types for each cpu family.
365 */
366 void cpu_list_available_types(void)
367 {
368 struct cpu_family *fp;
369 int iadd = DEBUG_INDENTATION;
370
371 fp = first_cpu_family;
372
373 if (fp == NULL) {
374 debug("No CPUs defined!\n");
375 return;
376 }
377
378 while (fp != NULL) {
379 debug("%s:\n", fp->name);
380 debug_indentation(iadd);
381 if (fp->list_available_types != NULL)
382 fp->list_available_types();
383 else
384 debug("(internal error: list_available_types"
385 " = NULL)\n");
386 debug_indentation(-iadd);
387
388 fp = fp->next;
389 }
390 }
391
392
393 /*
394 * cpu_run_deinit():
395 *
396 * Shuts down all CPUs in a machine when ending a simulation. (This function
397 * should only need to be called once for each machine.)
398 */
399 void cpu_run_deinit(struct machine *machine)
400 {
401 int te;
402
403 /*
404 * Two last ticks of every hardware device. This will allow
405 * framebuffers to draw the last updates to the screen before
406 * halting.
407 */
408 for (te=0; te<machine->n_tick_entries; te++) {
409 machine->tick_func[te](machine->cpus[0],
410 machine->tick_extra[te]);
411 machine->tick_func[te](machine->cpus[0],
412 machine->tick_extra[te]);
413 }
414
415 debug("cpu_run_deinit(): All CPUs halted.\n");
416
417 if (machine->show_nr_of_instructions || !quiet_mode)
418 cpu_show_cycles(machine, 1);
419
420 fflush(stdout);
421 }
422
423
424 /*
425 * cpu_show_cycles():
426 *
427 * If automatic adjustment of clock interrupts is turned on, then recalculate
428 * emulated_hz. Also, if show_nr_of_instructions is on, then print a
429 * line to stdout about how many instructions/cycles have been executed so
430 * far.
431 */
432 void cpu_show_cycles(struct machine *machine, int forced)
433 {
434 uint64_t offset, pc;
435 char *symbol;
436 int64_t mseconds, ninstrs, is, avg;
437 struct timeval tv;
438 int h, m, s, ms, d;
439
440 static int64_t mseconds_last = 0;
441 static int64_t ninstrs_last = -1;
442
443 pc = machine->cpus[machine->bootstrap_cpu]->pc;
444
445 gettimeofday(&tv, NULL);
446 mseconds = (tv.tv_sec - machine->starttime.tv_sec) * 1000
447 + (tv.tv_usec - machine->starttime.tv_usec) / 1000;
448
449 if (mseconds == 0)
450 mseconds = 1;
451
452 if (mseconds - mseconds_last == 0)
453 mseconds ++;
454
455 ninstrs = machine->ncycles_since_gettimeofday;
456
457 if (machine->automatic_clock_adjustment) {
458 static int first_adjustment = 1;
459
460 /* Current nr of cycles per second: */
461 int64_t cur_cycles_per_second = 1000 *
462 (ninstrs-ninstrs_last) / (mseconds-mseconds_last);
463
464 /* fatal("[ CYCLES PER SECOND = %"PRIi64" ]\n",
465 cur_cycles_per_second); */
466
467 if (cur_cycles_per_second < 1000000)
468 cur_cycles_per_second = 1000000;
469
470 if (first_adjustment) {
471 machine->emulated_hz = cur_cycles_per_second;
472 first_adjustment = 0;
473 } else {
474 machine->emulated_hz = (15 * machine->emulated_hz +
475 cur_cycles_per_second) / 16;
476 }
477
478 /* fatal("[ updating emulated_hz to %"PRIi64" Hz ]\n",
479 machine->emulated_hz); */
480 }
481
482
483 /* RETURN here, unless show_nr_of_instructions (-N) is turned on: */
484 if (!machine->show_nr_of_instructions && !forced)
485 goto do_return;
486
487 printf("[ %"PRIi64" instrs", (int64_t)machine->ncycles);
488
489 if (!machine->automatic_clock_adjustment) {
490 d = machine->emulated_hz / 1000;
491 if (d < 1)
492 d = 1;
493 ms = machine->ncycles / d;
494 h = ms / 3600000;
495 ms -= 3600000 * h;
496 m = ms / 60000;
497 ms -= 60000 * m;
498 s = ms / 1000;
499 ms -= 1000 * s;
500
501 printf(", emulated time = %02i:%02i:%02i.%03i; ", h, m, s, ms);
502 }
503
504 /* Instructions per second, and average so far: */
505 is = 1000 * (ninstrs-ninstrs_last) / (mseconds-mseconds_last);
506 avg = (long long)1000 * ninstrs / mseconds;
507 if (is < 0)
508 is = 0;
509 if (avg < 0)
510 avg = 0;
511 printf("; i/s=%"PRIi64" avg=%"PRIi64, is, avg);
512
513 symbol = get_symbol_name(&machine->symbol_context, pc, &offset);
514
515 if (machine->ncpus == 1) {
516 if (machine->cpus[machine->bootstrap_cpu]->is_32bit)
517 printf("; pc=0x%08"PRIx32, (uint32_t) pc);
518 else
519 printf("; pc=0x%016"PRIx64, (uint64_t) pc);
520 }
521
522 if (symbol != NULL)
523 printf(" <%s>", symbol);
524 printf(" ]\n");
525
526 do_return:
527 ninstrs_last = ninstrs;
528 mseconds_last = mseconds;
529 }
530
531
532 /*
533 * cpu_run_init():
534 *
535 * Prepare to run instructions on all CPUs in this machine. (This function
536 * should only need to be called once for each machine.)
537 */
538 void cpu_run_init(struct machine *machine)
539 {
540 int ncpus = machine->ncpus;
541 int te;
542
543 machine->a_few_cycles = 1048576;
544 machine->ncycles_flush = 0;
545 machine->ncycles = 0;
546 machine->ncycles_show = 0;
547
548 /*
549 * Instead of doing { one cycle, check hardware ticks }, we
550 * can do { n cycles, check hardware ticks }, as long as
551 * n is at most as much as the lowest number of cycles/tick
552 * for any hardware device.
553 */
554 for (te=0; te<machine->n_tick_entries; te++) {
555 if (machine->ticks_reset_value[te] < machine->a_few_cycles)
556 machine->a_few_cycles = machine->ticks_reset_value[te];
557 }
558
559 machine->a_few_cycles >>= 1;
560 if (machine->a_few_cycles < 1)
561 machine->a_few_cycles = 1;
562
563 if (ncpus > 1)
564 machine->a_few_cycles = 1;
565
566 /* debug("cpu_run_init(): a_few_cycles = %i\n",
567 machine->a_few_cycles); */
568
569 /* For performance measurement: */
570 gettimeofday(&machine->starttime, NULL);
571 machine->ncycles_since_gettimeofday = 0;
572 }
573
574
575 /*
576 * add_cpu_family():
577 *
578 * Allocates a cpu_family struct and calls an init function for the
579 * family to fill in reasonable data and pointers.
580 */
581 static void add_cpu_family(int (*family_init)(struct cpu_family *), int arch)
582 {
583 struct cpu_family *fp, *tmp;
584 int res;
585
586 fp = malloc(sizeof(struct cpu_family));
587 if (fp == NULL) {
588 fprintf(stderr, "add_cpu_family(): out of memory\n");
589 exit(1);
590 }
591 memset(fp, 0, sizeof(struct cpu_family));
592
593 /*
594 * family_init() returns 1 if the struct has been filled with
595 * valid data, 0 if suppor for the cpu family isn't compiled
596 * into the emulator.
597 */
598 res = family_init(fp);
599 if (!res) {
600 free(fp);
601 return;
602 }
603 fp->arch = arch;
604 fp->next = NULL;
605
606 /* Add last in family chain: */
607 tmp = first_cpu_family;
608 if (tmp == NULL) {
609 first_cpu_family = fp;
610 } else {
611 while (tmp->next != NULL)
612 tmp = tmp->next;
613 tmp->next = fp;
614 }
615 }
616
617
618 /*
619 * cpu_family_ptr_by_number():
620 *
621 * Returns a pointer to a CPU family based on the ARCH_* integers.
622 */
623 struct cpu_family *cpu_family_ptr_by_number(int arch)
624 {
625 struct cpu_family *fp;
626 fp = first_cpu_family;
627
628 /* YUCK! This is too hardcoded! TODO */
629
630 while (fp != NULL) {
631 if (arch == fp->arch)
632 return fp;
633 fp = fp->next;
634 }
635
636 return NULL;
637 }
638
639
640 /*
641 * cpu_init():
642 *
643 * Should be called before any other cpu_*() function.
644 */
645 void cpu_init(void)
646 {
647 /* Note: These are registered in alphabetic order. */
648
649 #ifdef ENABLE_ALPHA
650 add_cpu_family(alpha_cpu_family_init, ARCH_ALPHA);
651 #endif
652
653 #ifdef ENABLE_ARM
654 add_cpu_family(arm_cpu_family_init, ARCH_ARM);
655 #endif
656
657 #ifdef ENABLE_AVR
658 add_cpu_family(avr_cpu_family_init, ARCH_AVR);
659 #endif
660
661 #ifdef ENABLE_HPPA
662 add_cpu_family(hppa_cpu_family_init, ARCH_HPPA);
663 #endif
664
665 #ifdef ENABLE_I960
666 add_cpu_family(i960_cpu_family_init, ARCH_I960);
667 #endif
668
669 #ifdef ENABLE_IA64
670 add_cpu_family(ia64_cpu_family_init, ARCH_IA64);
671 #endif
672
673 #ifdef ENABLE_M68K
674 add_cpu_family(m68k_cpu_family_init, ARCH_M68K);
675 #endif
676
677 #ifdef ENABLE_MIPS
678 add_cpu_family(mips_cpu_family_init, ARCH_MIPS);
679 #endif
680
681 #ifdef ENABLE_PPC
682 add_cpu_family(ppc_cpu_family_init, ARCH_PPC);
683 #endif
684
685 #ifdef ENABLE_SH
686 add_cpu_family(sh_cpu_family_init, ARCH_SH);
687 #endif
688
689 #ifdef ENABLE_SPARC
690 add_cpu_family(sparc_cpu_family_init, ARCH_SPARC);
691 #endif
692
693 #ifdef ENABLE_X86
694 add_cpu_family(x86_cpu_family_init, ARCH_X86);
695 #endif
696 }
697
  ViewVC Help
Powered by ViewVC 1.1.26