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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (11 years, 11 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 <html><head><title>Gavare's eXperimental Emulator:&nbsp;&nbsp;&nbsp;Experimenting with GXemul</title>
2 <meta name="robots" content="noarchive,nofollow,noindex"></head>
3 <body bgcolor="#f8f8f8" text="#000000" link="#4040f0" vlink="#404040" alink="#ff0000">
4 <table border=0 width=100% bgcolor="#d0d0d0"><tr>
5 <td width=100% align=center valign=center><table border=0 width=100%><tr>
6 <td align="left" valign=center bgcolor="#d0efff"><font color="#6060e0" size="6">
7 <b>Gavare's eXperimental Emulator:</b></font><br>
8 <font color="#000000" size="6"><b>Experimenting with GXemul</b>
9 </font></td></tr></table></td></tr></table><p>
10
11 <!--
12
13 $Id: experiments.html,v 1.104 2006/10/07 01:40:33 debug Exp $
14
15 Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
16
17 Redistribution and use in source and binary forms, with or without
18 modification, are permitted provided that the following conditions are met:
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20 1. Redistributions of source code must retain the above copyright
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22 2. Redistributions in binary form must reproduce the above copyright
23 notice, this list of conditions and the following disclaimer in the
24 documentation and/or other materials provided with the distribution.
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26 derived from this software without specific prior written permission.
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41
42 <a href="./">Back to the index</a>
43
44 <p><br>
45 <h2>Experimenting with GXemul</h2>
46
47 <p>
48 <ul>
49 <li><a href="#hello">Hello world</a>
50 <li><a href="#expdevices">Experimental devices</a>
51 </ul>
52
53
54
55
56
57
58 <p><br>
59 <a name="hello"></a>
60 <h3>Hello world:</h3>
61
62 You might want to use the emulator to develop programs on your own,
63 not just run precompiled kernels such as NetBSD. To get started, I recommend
64 that you do two things:
65
66 <p>
67 <ul>
68 <li>Build and install a cross-compiler for your chosen target.
69 GCC is usually a good compiler choice, because it is portable
70 and in wide-spread use. (Other compilers should work too.)
71
72 <p>
73 <li>Compile the Hello World demo program for your chosen target, and run
74 it in the emulator.
75 </ul>
76
77 <p>The Hello World demo program is included in the GXemul source
78 code distribution, in the <a href="../demos/hello/"><tt>demos/hello/</tt></a>
79 subdirectory. The README files in the demo directories have several
80 examples of how the demo programs can be built.
81
82 <p>Hopefully this is enough to get you inspired. :-)
83
84
85
86
87
88
89 <p><br>
90 <a name="expdevices"></a>
91 <h3>Experimental devices:</h3>
92
93 The emulator has several modes where it doesn't emulate any real machine.
94 It can either run in "bare" mode, where no devices are included by default
95 (just the CPU), or in a "test" mode where some simple devices are
96 emulated.
97
98 <p>The test machines (<tt>testmips</tt>, <tt>testppc</tt>, etc) have the
99 following experimental devices:
100
101 <p>
102 <center><table border="0" width="80%">
103
104 <tr>
105 <td align="left" valign="top" width="200">
106 <a name="expdevices_cons"><b><tt>cons</tt>:</b></a>
107 <p>A simple console device, for writing
108 characters to the controlling terminal
109 and receiving keypresses.
110 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_cons.c</tt></font>
111 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_cons.h</tt></font>
112 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x10000000</font>
113 </td>
114 <td align="left" valign="top" width="25">&nbsp;</td>
115 <td align="left" valign="top">
116 <table border="0">
117 <tr>
118 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
119 <td align="left" valign="top"><i><u>Effect:</u></i></td>
120 </tr>
121 <tr>
122 <td align="left" valign="top"><tt>0x00</tt></td>
123 <td align="left" valign="top">
124 Read: <b><tt>getchar()</tt></b> (non-blocking; returns
125 <tt>0</tt> if no char was available)<br>
126 Write: <b><tt>putchar(ch)</tt></b></td>
127 </tr>
128 <tr>
129 <td align="left" valign="top"><tt>0x10</tt></td>
130 <td align="left" valign="top">Read or write: <b><tt>halt()</tt></b><br>
131 (Useful for exiting the emulator.)</td>
132 </tr>
133 </table>
134 </td>
135 </tr>
136
137 <tr height="15">
138 <td height="15">&nbsp;</td>
139 </tr>
140
141 <tr>
142 <td align="left" valign="top">
143 <a name="expdevices_mp"><b><tt>mp</tt>:</b></a>
144 <p>This device controls the behaviour of CPUs in an emulated
145 multi-processor system.
146 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_mp.c</tt></font>
147 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_mp.h</tt></font>
148 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x11000000</font>
149 </td>
150 <td></td>
151 <td align="left" valign="top">
152 <table border="0">
153 <tr>
154 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
155 <td align="left" valign="top"><i><u>Effect:</u></i></td>
156 </tr>
157 <tr>
158 <td align="left" valign="top"><tt>0x0000</tt></td>
159 <td align="left" valign="top">Read: <b><tt>whoami()</tt></b>.
160 Returns the id of the CPU doing the read.</td>
161 </tr>
162 <tr>
163 <td align="left" valign="top"><tt>0x0010</tt></td>
164 <td align="left" valign="top">Read: <b><tt>ncpus()</tt></b>.
165 Returns the number of CPUs in the system.</td>
166 </tr>
167 <tr>
168 <td align="left" valign="top"><tt>0x0020</tt></td>
169 <td align="left" valign="top">Write: <b><tt>startupcpu(i)</tt></b>.
170 Starts CPU i. It begins execution at the address
171 set by a write to startupaddr (see below).</td>
172 </tr>
173 <tr>
174 <td align="left" valign="top"><tt>0x0030</tt></td>
175 <td align="left" valign="top">Write: <b><tt>startupaddr(addr)</tt></b>.
176 Sets the starting address for CPUs.</td>
177 </tr>
178 <tr>
179 <td align="left" valign="top"><tt>0x0040</tt></td>
180 <td align="left" valign="top">Write: <b><tt>pause_addr(addr)</tt></b>.
181 Sets the pause address. (NOTE: This is not
182 used anymore.)</td>
183 </tr>
184 <tr>
185 <td align="left" valign="top"><tt>0x0050</tt></td>
186 <td align="left" valign="top">Write: <b><tt>pause_cpu(i)</tt></b>.
187 Pauses all CPUs <i>except</i> CPU i.</td>
188 </tr>
189 <tr>
190 <td align="left" valign="top"><tt>0x0060</tt></td>
191 <td align="left" valign="top">Write: <b><tt>unpause_cpu(i)</tt></b>.
192 Unpauses CPU i.</td>
193 </tr>
194 <tr>
195 <td align="left" valign="top"><tt>0x0070</tt></td>
196 <td align="left" valign="top">Write: <b><tt>startupstack(addr)</tt></b>.
197 Sets the startup stack address. (CPUs started with
198 startupcpu() above will have their stack pointer
199 set to this value.)</td>
200 </tr>
201 <tr>
202 <td align="left" valign="top"><tt>0x0080</tt></td>
203 <td align="left" valign="top">Read: <b><tt>hardware_random()</tt></b>.
204 This produces a "random" number.</td>
205 </tr>
206 <tr>
207 <td align="left" valign="top"><tt>0x0090</tt></td>
208 <td align="left" valign="top">Read: <b><tt>memory()</tt></b>.
209 Returns the number of bytes of RAM in the system.</td>
210 </tr>
211 <tr>
212 <td align="left" valign="top"><tt>0x00a0</tt></td>
213 <td align="left" valign="top">Write: <b><tt>ipi_one((nr &lt;&lt; 16) + cpuid)</tt></b>.
214 Sends IPI <tt>nr</tt> to a specific CPU.</td>
215 </tr>
216 <tr>
217 <td align="left" valign="top"><tt>0x00b0</tt></td>
218 <td align="left" valign="top">Write: <b><tt>ipi_many((nr &lt;&lt; 16) + cpuid)</tt></b>.
219 Sends IPI <tt>nr</tt> to all CPUs <i>except</i>
220 the specified one.</td>
221 </tr>
222 <tr>
223 <td align="left" valign="top"><tt>0x00c0</tt></td>
224 <td align="left" valign="top">Read: <b><tt>ipi_read()</tt></b>.
225 Returns the next pending IPI. 0 is returned if there is no
226 pending IPI (so 0 shouldn't be used for valid IPIs).
227 Hardware int 6 is deasserted when the IPI queue is empty.
228 <br>Write: <b><tt>ipi_flush()</tt></b>.
229 Clears the IPI queue, discarding any pending IPIs.</td>
230 </tr>
231 <tr>
232 <td align="left" valign="top"><tt>0x00d0</tt></td>
233 <td align="left" valign="top">Read: <b><tt>ncycles()</tt></b>.
234 Returns approximately the number of cycles executed.
235 Note: this value is not updated for every instruction,
236 so it cannot be used for small measurements.</td>
237 </tr>
238 </table>
239 </td>
240 </tr>
241
242 <tr height="15">
243 <td height="15">&nbsp;</td>
244 </tr>
245
246 <tr>
247 <td align="left" valign="top">
248 <a name="expdevices_fb"><b><tt>fb</tt>:</b></a>
249 <p>A simple linear framebuffer, for graphics output.
250 640 x 480 pixels, 3 bytes per pixel (red, green, blue, 8 bits each).
251 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_fb.c</tt></font>
252 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_fb.h</tt></font>
253 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x12000000</font>
254 </td>
255 <td></td>
256 <td align="left" valign="top">
257 <table border="0">
258 <tr>
259 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
260 <td align="left" valign="top"><i><u>Effect:</u></i></td>
261 </tr>
262 <tr>
263 <td align="left" valign="top"><tt>0x00000-</tt><br><tt>0xe0fff</tt></td>
264 <td align="left" valign="top">Read: read pixel values.
265 <br>Write: write pixel values.</td>
266 </tr>
267 </table>
268 </td>
269 </tr>
270
271 <tr height="15">
272 <td height="15">&nbsp;</td>
273 </tr>
274
275 <tr>
276 <td align="left" valign="top">
277 <a name="expdevices_disk"><b><tt>disk</tt>:</b></a>
278 <p>Disk controller, which can read from and write
279 to emulated IDE disks. It does not use interrupts; read and
280 write operations finish instantaneously.
281 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_disk.c</tt></font>
282 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_disk.h</tt></font>
283 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x13000000</font>
284 </td>
285 <td></td>
286 <td align="left" valign="top">
287 <table border="0">
288 <tr>
289 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
290 <td align="left" valign="top"><i><u>Effect:</u></i></td>
291 </tr>
292 <tr>
293 <td align="left" valign="top"><tt>0x0000</tt></td>
294 <td align="left" valign="top">Write: Set the offset (in bytes) from the beginning
295 of the disk image. This offset will be used for the next read/write operation.</td>
296 </tr>
297 <tr>
298 <td align="left" valign="top"><tt>0x0010</tt></td>
299 <td align="left" valign="top">Write: Select the IDE ID to be used in the next
300 read/write operation.</td>
301 </tr>
302 <tr>
303 <td align="left" valign="top"><tt>0x0020</tt></td>
304 <td align="left" valign="top">Write: Start a read or write operation.
305 (Writing <tt>0</tt> means a Read operation, a <tt>1</tt> means a
306 Write operation.)</td>
307 </tr>
308 <tr>
309 <td align="left" valign="top"><tt>0x0030</tt></td>
310 <td align="left" valign="top">Read: Get status of the last operation.
311 (Status 0 means failure, non-zero means success.)</td>
312 </tr>
313 <tr>
314 <td align="left" valign="top"><tt>0x4000-</tt><br><tt>0x41ff</tt>&nbsp;&nbsp;&nbsp;</td>
315 <td align="left" valign="top">Read/Write: 512 bytes data buffer.</td>
316 </tr>
317 </table>
318 </td>
319 </tr>
320
321 <tr height="15">
322 <td height="15">&nbsp;</td>
323 </tr>
324
325 <tr>
326 <td align="left" valign="top">
327 <a name="expdevices_ether"><b><tt>ether</tt>:</b></a>
328 <p>A simple ethernet controller, enough to send
329 and receive packets on a simulated network.
330 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_ether.c</tt></font>
331 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_ether.h</tt></font>
332 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x14000000</font>
333 </td>
334 <td></td>
335 <td align="left" valign="top">
336 <table border="0">
337 <tr>
338 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
339 <td align="left" valign="top"><i><u>Effect:</u></i></td>
340 </tr>
341 <tr>
342 <td align="left" valign="top"><tt>0x0000-</tt><br><tt>0x3fff</tt></td>
343 <td align="left" valign="top">Read/write buffer for the packet to be sent/received.</td>
344 </tr>
345 <tr>
346 <td align="left" valign="top"><tt>0x4000</tt></td>
347 <td align="left" valign="top">Read: status word, one or more of these:
348 <br><tt>0x01</tt>&nbsp;=&nbsp;something was received (because of
349 the last command)
350 <br><tt>0x02</tt>&nbsp;=&nbsp;more packets are available
351 <br><i>NOTE:</i> Whenever the status word is non-zero,
352 an interrupt is asserted. Reading the status word
353 clears it, and deasserts the interrupt.</td>
354 </tr>
355 <tr>
356 <td align="left" valign="top"><tt>0x4010</tt></td>
357 <td align="left" valign="top">Read: get the Length of the received packet
358 <br>Write: set the Length of the next packet to transmit</td>
359 </tr>
360 <tr>
361 <td align="left" valign="top"><tt>0x4020</tt></td>
362 <td align="left" valign="top">Write: command:
363 <br><tt>0x00:</tt>&nbsp;receive a packet
364 <br><tt>0x01:</tt>&nbsp;send a packet</td>
365 </tr>
366 </table>
367 </td>
368 </tr>
369
370 <tr height="15">
371 <td height="15">&nbsp;</td>
372 </tr>
373
374 <tr>
375 <td align="left" valign="top">
376 <a name="expdevices_rtc"><b><tt>rtc</tt>:</b></a>
377 <p>A Real-Time Clock, used to retrieve the current time
378 and to cause periodic interrupts.
379 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_rtc.c</tt></font>
380 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_rtc.h</tt></font>
381 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x15000000</font>
382 </td>
383 <td></td>
384 <td align="left" valign="top">
385 <table border="0">
386 <tr>
387 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
388 <td align="left" valign="top"><i><u>Effect:</u></i></td>
389 </tr>
390 <tr>
391 <td align="left" valign="top"><tt>0x0000</tt></td>
392 <td align="left" valign="top">Read or Write: Trigger a clock update (a gettimeofday() on the host).</td>
393 </tr>
394 <tr>
395 <td align="left" valign="top"><tt>0x0010</tt></td>
396 <td align="left" valign="top">Read: Seconds since 1st January 1970</td>
397 </tr>
398 <tr>
399 <td align="left" valign="top"><tt>0x0020</tt></td>
400 <td align="left" valign="top">Read: Microseconds</td>
401 </tr>
402 <tr>
403 <td align="left" valign="top"><tt>0x0100</tt></td>
404 <td align="left" valign="top">Read: Get the current
405 timer interrupt frequency.<br>Write: Set the timer
406 interrupt frequency. (Writing 0 disables the timer.)</td>
407 </tr>
408 <tr>
409 <td align="left" valign="top"><tt>0x0110</tt></td>
410 <td align="left" valign="top">Read or Write: Acknowledge
411 one timer interrupt. (Note that if multiple interrupts
412 are pending, only one is acknowledged.)</td>
413 </tr>
414 </table>
415 </td>
416 </tr>
417
418 </table></center>
419
420 <p>
421 While these devices may resemble real-world hardware, they are
422 intentionally made simpler to use. (An exception is the framebuffer;
423 some machines actually have simple linear framebuffers like this.)
424
425 <p>If the physical address is <tt>0x10000000</tt>, then for MIPS that
426 means that it can be accessed at virtual address
427 <tt>0xffffffffb0000000</tt>. (Actually it can be accessed at
428 <tt>0xffffffff90000000</tt> too, but devices should usually be accessed in
429 a non-cached manner.)
430
431 <p>When using the Alpha, ARM, or PPC test machines, the addresses are
432 <tt>0x10000000</tt>, <tt>0x11000000</tt> etc., so no need to add any
433 virtual displacement.
434
435 <p>The <tt>mp</tt>, <tt>disk</tt>, and <tt>ether</tt> devices are agnostic
436 when it comes to word-length. For example, when reading offset
437 <tt>0x0000</tt> of the <tt>mp</tt> device, you may use any kind of read
438 (an 8-bit read will work just as well as a 64-bit read, although the value
439 will be truncated to 8 bits in the first case). You can <i>not</i>,
440 however, read one byte from <tt>0x0000</tt> and one from <tt>0x0001</tt>,
441 and combine the result. The read from <tt>0x0001</tt> will be invalid.
442
443 <p>The <tt>cons</tt> device should be accessed using 8-bit reads
444 and writes. Doing a getchar() (ie reading from offset <tt>0x00</tt>)
445 returns <tt>0</tt> if no character was available. Whenever a character is
446 available, the <tt>cons</tt> device' interrupt is asserted. When there are
447 no more available characters, the interrupt is deasserted. (Remember that
448 the interrupt has to be unmasked to be able to actually cause an
449 interrupt.)
450
451 <p>IPIs (inter-processor interrupts) are controlled by the <tt>mp</tt>
452 device. Whenever an IPI is "sent" from a source to one or more target
453 CPUs, the interrupt is asserted on the target CPUs, and the IPI number is
454 added last in the IPI queue for each of the target CPUs. It is then up to
455 those CPUs to individually read from offset <tt>0x00c0</tt>, to figure out
456 what kind of IPI it was.
457
458
459
460 <p>Interrupt mappings are as follows:
461
462 <p><center>
463 <table border="1">
464 <tr><td align="center">
465 <b><tt>testmips</tt></b>
466 </td></tr>
467 <tr><td>
468 <table border="0">
469 <tr><td align="center">IRQ:</td><td>&nbsp;</td>
470 <td>Used for:</td></tr>
471 <tr><td align="center">7</td><td></td>
472 <td>MIPS count/compare interrupt</td></tr>
473 <tr><td align="center">6</td><td></td>
474 <td><tt>mp</tt> (inter-processor interrupts)</td></tr>
475 <tr><td align="center">4</td><td></td>
476 <td><tt>rtc</tt></td></tr>
477 <tr><td align="center">3</td><td></td>
478 <td><tt>ether</tt></td></tr>
479 <tr><td align="center">2</td><td></td>
480 <td><tt>cons</tt></td></tr>
481 </table>
482 </td></tr>
483 </table>
484 </center>
485
486 <p>Other machines: TODO
487
488
489 <p><br>
490
491
492
493 </p>
494
495 </body>
496 </html>

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