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Mon Oct 8 16:19:56 2007 UTC (13 years, 1 month ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 <html><head><title>Gavare's eXperimental Emulator:&nbsp;&nbsp;&nbsp;Experimenting with GXemul</title>
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3 <body bgcolor="#f8f8f8" text="#000000" link="#4040f0" vlink="#404040" alink="#ff0000">
4 <table border=0 width=100% bgcolor="#d0d0d0"><tr>
5 <td width=100% align=center valign=center><table border=0 width=100%><tr>
6 <td align="left" valign=center bgcolor="#d0efff"><font color="#6060e0" size="6">
7 <b>Gavare's eXperimental Emulator:</b></font><br>
8 <font color="#000000" size="6"><b>Experimenting with GXemul</b>
9 </font></td></tr></table></td></tr></table><p>
10
11 <!--
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13 $Id: experiments.html,v 1.102 2006/06/12 10:21:12 debug Exp $
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15 Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
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18 modification, are permitted provided that the following conditions are met:
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41
42 <a href="./">Back to the index</a>
43
44 <p><br>
45 <h2>Experimenting with GXemul</h2>
46
47 <p>
48 <ul>
49 <li><a href="#hello">Hello world</a>
50 <li><a href="#expdevices">Experimental devices</a>
51 </ul>
52
53
54
55
56
57
58 <p><br>
59 <a name="hello"></a>
60 <h3>Hello world:</h3>
61
62 You might want to use the emulator to develop programs on your own,
63 not just run precompiled kernels such as NetBSD. To get started, I recommend
64 that you do two things:
65
66 <p>
67 <ul>
68 <li>Build and install a cross-compiler for your chosen target.
69 GCC is usually a good compiler choice, because it is portable
70 and in wide-spread use. (Other compilers should work too.)
71
72 <p>
73 <li>Compile the Hello World demo program for your chosen target, and run
74 it in the emulator.
75 </ul>
76
77 <p>The Hello World demo program is included in the GXemul source
78 code distribution, in the <a href="../demos/hello/"><tt>demos/hello/</tt></a>
79 subdirectory. The README files in the demo directories have several
80 examples of how the demo programs can be built.
81
82 <p>Hopefully this is enough to get you inspired. :-)
83
84
85
86
87
88
89 <p><br>
90 <a name="expdevices"></a>
91 <h3>Experimental devices:</h3>
92
93 The emulator has several modes where it doesn't emulate any real machine.
94 It can either run in "bare" mode, where no devices are included by default
95 (just the CPU), or in a "test" mode where some simple devices are
96 emulated.
97
98 <p>The test machines (<tt>testmips</tt>, <tt>testppc</tt>, etc) have the
99 following experimental devices:
100
101 <p>
102 <center><table border="0" width="80%">
103
104 <tr>
105 <td align="left" valign="top" width="200">
106 <a name="expdevices_cons"><b><tt>cons</tt>:</b></a>
107 <p>A simple console device, for writing
108 characters to the controlling terminal
109 and receiving keypresses.
110 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_cons.c</tt></font>
111 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_cons.h</tt></font>
112 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x10000000</font>
113 </td>
114 <td align="left" valign="top" width="25">&nbsp;</td>
115 <td align="left" valign="top">
116 <table border="0">
117 <tr>
118 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
119 <td align="left" valign="top"><i><u>Effect:</u></i></td>
120 </tr>
121 <tr>
122 <td align="left" valign="top"><tt>0x00</tt></td>
123 <td align="left" valign="top">
124 Read: <b><tt>getchar()</tt></b> (non-blocking; returns
125 <tt>0</tt> if no char was available)<br>
126 Write: <b><tt>putchar(ch)</tt></b></td>
127 </tr>
128 <tr>
129 <td align="left" valign="top"><tt>0x10</tt></td>
130 <td align="left" valign="top">Read or write: <b><tt>halt()</tt></b><br>
131 (Useful for exiting the emulator.)</td>
132 </tr>
133 </table>
134 </td>
135 </tr>
136
137 <tr height="15">
138 <td height="15">&nbsp;</td>
139 </tr>
140
141 <tr>
142 <td align="left" valign="top">
143 <a name="expdevices_mp"><b><tt>mp</tt>:</b></a>
144 <p>This device controls the behaviour of CPUs in an emulated
145 multi-processor system.
146 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_mp.c</tt></font>
147 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_mp.h</tt></font>
148 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x11000000</font>
149 </td>
150 <td></td>
151 <td align="left" valign="top">
152 <table border="0">
153 <tr>
154 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
155 <td align="left" valign="top"><i><u>Effect:</u></i></td>
156 </tr>
157 <tr>
158 <td align="left" valign="top"><tt>0x0000</tt></td>
159 <td align="left" valign="top">Read: <b><tt>whoami()</tt></b>.
160 Returns the id of the CPU doing the read.</td>
161 </tr>
162 <tr>
163 <td align="left" valign="top"><tt>0x0010</tt></td>
164 <td align="left" valign="top">Read: <b><tt>ncpus()</tt></b>.
165 Returns the number of CPUs in the system.</td>
166 </tr>
167 <tr>
168 <td align="left" valign="top"><tt>0x0020</tt></td>
169 <td align="left" valign="top">Write: <b><tt>startupcpu(i)</tt></b>.
170 Starts CPU i. It begins execution at the address
171 set by a write to startupaddr (see below).</td>
172 </tr>
173 <tr>
174 <td align="left" valign="top"><tt>0x0030</tt></td>
175 <td align="left" valign="top">Write: <b><tt>startupaddr(addr)</tt></b>.
176 Sets the starting address for CPUs.</td>
177 </tr>
178 <tr>
179 <td align="left" valign="top"><tt>0x0040</tt></td>
180 <td align="left" valign="top">Write: <b><tt>pause_addr(addr)</tt></b>.
181 Sets the pause address. (NOTE: This is not
182 used anymore.)</td>
183 </tr>
184 <tr>
185 <td align="left" valign="top"><tt>0x0050</tt></td>
186 <td align="left" valign="top">Write: <b><tt>pause_cpu(i)</tt></b>.
187 Pauses all CPUs <i>except</i> CPU i.</td>
188 </tr>
189 <tr>
190 <td align="left" valign="top"><tt>0x0060</tt></td>
191 <td align="left" valign="top">Write: <b><tt>unpause_cpu(i)</tt></b>.
192 Unpauses CPU i.</td>
193 </tr>
194 <tr>
195 <td align="left" valign="top"><tt>0x0070</tt></td>
196 <td align="left" valign="top">Write: <b><tt>startupstack(addr)</tt></b>.
197 Sets the startup stack address. (CPUs started with
198 startupcpu() above will have their stack pointer
199 set to this value.)</td>
200 </tr>
201 <tr>
202 <td align="left" valign="top"><tt>0x0080</tt></td>
203 <td align="left" valign="top">Read: <b><tt>hardware_random()</tt></b>.
204 This produces a "random" number.</td>
205 </tr>
206 <tr>
207 <td align="left" valign="top"><tt>0x0090</tt></td>
208 <td align="left" valign="top">Read: <b><tt>memory()</tt></b>.
209 Returns the number of bytes of RAM in the system.</td>
210 </tr>
211 <tr>
212 <td align="left" valign="top"><tt>0x00a0</tt></td>
213 <td align="left" valign="top">Write: <b><tt>ipi_one((nr &lt;&lt; 16) + cpuid)</tt></b>.
214 Sends IPI <tt>nr</tt> to a specific CPU.</td>
215 </tr>
216 <tr>
217 <td align="left" valign="top"><tt>0x00b0</tt></td>
218 <td align="left" valign="top">Write: <b><tt>ipi_many((nr &lt;&lt; 16) + cpuid)</tt></b>.
219 Sends IPI <tt>nr</tt> to all CPUs <i>except</i>
220 the specified one.</td>
221 </tr>
222 <tr>
223 <td align="left" valign="top"><tt>0x00c0</tt></td>
224 <td align="left" valign="top">Read: <b><tt>ipi_read()</tt></b>.
225 Returns the next pending IPI. 0 is returned if there is no
226 pending IPI (so 0 shouldn't be used for valid IPIs).
227 Hardware int 6 is deasserted when the IPI queue is empty.
228 <br>Write: <b><tt>ipi_flush()</tt></b>.
229 Clears the IPI queue, discarding any pending IPIs.</td>
230 </tr>
231 <tr>
232 <td align="left" valign="top"><tt>0x00d0</tt></td>
233 <td align="left" valign="top">Read: <b><tt>ncycles()</tt></b>.
234 Returns approximately the number of cycles executed.
235 Note: this value is not updated for every instruction,
236 so it cannot be used for small measurements.</td>
237 </tr>
238 </table>
239 </td>
240 </tr>
241
242 <tr height="15">
243 <td height="15">&nbsp;</td>
244 </tr>
245
246 <tr>
247 <td align="left" valign="top">
248 <a name="expdevices_fb"><b><tt>fb</tt>:</b></a>
249 <p>A simple linear framebuffer, for graphics output.
250 640 x 480 pixels, 3 bytes per pixel (red, green, blue, 8 bits each).
251 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_fb.c</tt></font>
252 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_fb.h</tt></font>
253 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x12000000</font>
254 </td>
255 <td></td>
256 <td align="left" valign="top">
257 <table border="0">
258 <tr>
259 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
260 <td align="left" valign="top"><i><u>Effect:</u></i></td>
261 </tr>
262 <tr>
263 <td align="left" valign="top"><tt>0x00000-</tt><br><tt>0xe0fff</tt></td>
264 <td align="left" valign="top">Read: read pixel values.
265 <br>Write: write pixel values.</td>
266 </tr>
267 </table>
268 </td>
269 </tr>
270
271 <tr height="15">
272 <td height="15">&nbsp;</td>
273 </tr>
274
275 <tr>
276 <td align="left" valign="top">
277 <a name="expdevices_disk"><b><tt>disk</tt>:</b></a>
278 <p>Disk controller, which can read from and write
279 to emulated IDE disks. It does not use interrupts; read and
280 write operations finish instantaneously.
281 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_disk.c</tt></font>
282 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_disk.h</tt></font>
283 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x13000000</font>
284 </td>
285 <td></td>
286 <td align="left" valign="top">
287 <table border="0">
288 <tr>
289 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
290 <td align="left" valign="top"><i><u>Effect:</u></i></td>
291 </tr>
292 <tr>
293 <td align="left" valign="top"><tt>0x0000</tt></td>
294 <td align="left" valign="top">Write: Set the offset (in bytes) from the beginning
295 of the disk image. This offset will be used for the next read/write operation.</td>
296 </tr>
297 <tr>
298 <td align="left" valign="top"><tt>0x0010</tt></td>
299 <td align="left" valign="top">Write: Select the IDE ID to be used in the next
300 read/write operation.</td>
301 </tr>
302 <tr>
303 <td align="left" valign="top"><tt>0x0020</tt></td>
304 <td align="left" valign="top">Write: Start a read or write operation.
305 (Writing <tt>0</tt> means a Read operation, a <tt>1</tt> means a
306 Write operation.)</td>
307 </tr>
308 <tr>
309 <td align="left" valign="top"><tt>0x0030</tt></td>
310 <td align="left" valign="top">Read: Get status of the last operation.
311 (Status 0 means failure, non-zero means success.)</td>
312 </tr>
313 <tr>
314 <td align="left" valign="top"><tt>0x4000-</tt><br><tt>0x41ff</tt>&nbsp;&nbsp;&nbsp;</td>
315 <td align="left" valign="top">Read/Write: 512 bytes data buffer.</td>
316 </tr>
317 </table>
318 </td>
319 </tr>
320
321 <tr height="15">
322 <td height="15">&nbsp;</td>
323 </tr>
324
325 <tr>
326 <td align="left" valign="top">
327 <a name="expdevices_ether"><b><tt>ether</tt>:</b></a>
328 <p>A simple ethernet controller, enough to send
329 and receive packets on a simulated network.
330 <p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_ether.c</tt></font>
331 <p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_ether.h</tt></font>
332 <br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x14000000</font>
333 </td>
334 <td></td>
335 <td align="left" valign="top">
336 <table border="0">
337 <tr>
338 <td align="left" valign="top"><i><u>Offset:</u></i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
339 <td align="left" valign="top"><i><u>Effect:</u></i></td>
340 </tr>
341 <tr>
342 <td align="left" valign="top"><tt>0x0000-</tt><br><tt>0x3fff</tt></td>
343 <td align="left" valign="top">Read/write buffer for the packet to be sent/received.</td>
344 </tr>
345 <tr>
346 <td align="left" valign="top"><tt>0x4000</tt></td>
347 <td align="left" valign="top">Read: status word, one or more of these:
348 <br><tt>0x01</tt>&nbsp;=&nbsp;something was received (because of
349 the last command)
350 <br><tt>0x02</tt>&nbsp;=&nbsp;more packets are available
351 <br><i>NOTE:</i> Whenever the status word is non-zero,
352 an interrupt is asserted. Reading the status word
353 clears it, and deasserts the interrupt.</td>
354 </tr>
355 <tr>
356 <td align="left" valign="top"><tt>0x4010</tt></td>
357 <td align="left" valign="top">Read: get the Length of the received packet
358 <br>Write: set the Length of the next packet to transmit</td>
359 </tr>
360 <tr>
361 <td align="left" valign="top"><tt>0x4020</tt></td>
362 <td align="left" valign="top">Write: command:
363 <br><tt>0x00:</tt>&nbsp;receive a packet
364 <br><tt>0x01:</tt>&nbsp;send a packet</td>
365 </tr>
366 </table>
367 </td>
368 </tr>
369
370 </table></center>
371
372 <p>
373 While these devices may resemble real-world hardware, they are
374 intentionally made simpler to use. (An exception is the framebuffer;
375 some machines actually have simple linear framebuffers like this.)
376
377 <p>If the physical address is <tt>0x10000000</tt>, then for MIPS that
378 means that it can be accessed at virtual address
379 <tt>0xffffffffb0000000</tt>. (Actually it can be accessed at
380 <tt>0xffffffff90000000</tt> too, but devices should usually be accessed in
381 a non-cached manner.)
382
383 <p>When using the Alpha, ARM, or PPC test machines, the addresses are
384 <tt>0x10000000</tt>, <tt>0x11000000</tt> etc., so no need to add any
385 virtual displacement.
386
387 <p>The <tt>mp</tt>, <tt>disk</tt>, and <tt>ether</tt> devices are agnostic
388 when it comes to word-length. For example, when reading offset
389 <tt>0x0000</tt> of the <tt>mp</tt> device, you may use any kind of read
390 (an 8-bit read will work just as well as a 64-bit read, although the value
391 will be truncated to 8 bits in the first case). You can <i>not</i>,
392 however, read one byte from <tt>0x0000</tt> and one from <tt>0x0001</tt>,
393 and combine the result. The read from <tt>0x0001</tt> will be invalid.
394
395 <p>The <tt>cons</tt> device should be accessed using 8-bit reads
396 and writes. Doing a getchar() (ie reading from offset <tt>0x00</tt>)
397 returns <tt>0</tt> if no character was available. Whenever a character is
398 available, the <tt>cons</tt> device' interrupt is asserted. When there are
399 no more available characters, the interrupt is deasserted. (Remember that
400 the interrupt has to be unmasked to be able to actually cause an
401 interrupt.)
402
403 <p>IPIs (inter-processor interrupts) are controlled by the <tt>mp</tt>
404 device. Whenever an IPI is "sent" from a source to one or more target
405 CPUs, the interrupt is asserted on the target CPUs, and the IPI number is
406 added last in the IPI queue for each of the target CPUs. It is then up to
407 those CPUs to individually read from offset <tt>0x00c0</tt>, to figure out
408 what kind of IPI it was.
409
410
411
412 <p>Interrupt mappings are as follows:
413
414 <p><center>
415 <table border="1">
416 <tr><td align="center">
417 <b><tt>testmips</tt></b>
418 </td></tr>
419 <tr><td>
420 <table border="0">
421 <tr><td align="center">IRQ:</td><td>&nbsp;</td>
422 <td>Used for:</td></tr>
423 <tr><td align="center">7</td><td></td>
424 <td>MIPS count/compare interrupt</td></tr>
425 <tr><td align="center">6</td><td></td>
426 <td><tt>mp</tt> (inter-processor interrupts)</td></tr>
427 <tr><td align="center">3</td><td></td>
428 <td><tt>ether</tt></td></tr>
429 <tr><td align="center">2</td><td></td>
430 <td><tt>cons</tt></td></tr>
431 </table>
432 </td></tr>
433 </table>
434 </center>
435
436 <p>Other machines: TODO
437
438
439 <p><br>
440
441
442
443 </p>
444
445 </body>
446 </html>

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