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Revision 12 - (hide annotations)
Mon Oct 8 16:18:38 2007 UTC (13 years, 3 months ago) by dpavlin
File size: 7143 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============

1 dpavlin 12 $Id: TODO,v 1.166 2005/08/16 05:44:33 debug Exp $
2 dpavlin 2
3 dpavlin 12 ===============================================================================
4 dpavlin 2
5 dpavlin 12 High priority stuff:
8     MIPS bintrans:
9     x) call/return address cache?
11     dyntrans:
12     x) memory write protection for ARM, but NOT for Alpha (because
13     it has the IMB instruction... hm)
15     x) call/return address cache
17     x) instr_call sequence analysis support? (Useful for
18     handtuning combinations.)
20     x) opcode statistics support?
21     TODO: is instr_call statistics enough?
23     x) support for archs that allow transparent unaligned load/stores
25     x) SMP: detect when an instruction such as ll/sc or cas is used,
26     and "synchronize" approximately the number of executed instructions
27     (or cycles) across all CPUs.
29     x) support for variable-length instructions (x86, m68k, ...)
30     Perhaps: don't increase the next_ic between every
31     instruction, but let each instruction's handler do
32     that for itself.
33     Problem: what about instructions crossing a (virtual)
34     page boundary? They cannot be translated once
35     and for all :( and must be interpreted slowly!
37     x) support for THUMB or MIPS16 (arm, mips)
39     x) support for Delay slots! (mips, sparc, hppa)
41     x) Alpha: hahaha, zapnot and inserts/extracts don't
42     compile into very nice code :-| fix this
44     x) 64-bit virtual memory translation tables (PPC, etc)
46     x) x86: convert to dyntrans. LOTS of stuff to consider.
49     ===============================================================================
51     Lower priority, but still important:
53     Redesign the entire "mainbus" concept:
54     o) Easily configurable interrupt routing in SMP systems.
55     o) Specific clock/bus speeds, cpu speeds etc.
56     o) Synchronization over network?
58 dpavlin 2 Caches / memory hierarchies: (this is mostly MIPS-specific)
59     o) MIPS coproc.c: bits in config registers should reflect
60     correct cache sizes for _all_ CPU types. (currently only
61     implemented for R4000, R1x000, and a few others)
62     o) src/memory*.c: Implement correct cache emulation for
63     all CPU types. (currently only R2000/R3000 is implemented)
64     (per CPU, multiple levels should be possible,
65     associativity etc!)
66     o) R2000/R3000 isn't _100%_ correct, just almost correct :)
67     o) Move the -S (fill mem with random) functionality into the
68     memory.c subsystem, not machine.c or wherever it is now
69     o) ECC stuff, simulation of memory errors? (Machine dependant)
70     o) More than 4GB of emulated RAM, when run on a 32-bit host?
71     (using manual swap-out of blocks to disk, ugly)
72     o) A global command line option should be used to turn
73     cache emulation on or off. When off, caches should be
74     faked like they are right now. When on, caches and
75     memory latencies should be emulated as correctly as
76     possible.
78     Network layer:
79     o) Multiple networks per emulation, and let different
80     NICs in machines connect to different networks.
81     o) many other issues: see src/net.c
83     MIPS CPU emulation:
84 dpavlin 12 o) i386 bintrans backend: movn etc, slt[u] for
85     64-bit mode, 64-bit shifts etc
86 dpavlin 2 o) Instructions:
87 dpavlin 12 o) All ISAs:
88 dpavlin 2 o) Floating point exception handling, and
89     add more instructions.
90     o) Finish the MIPS16 translator, and test it!
91     o) MIPS ISA I, II, III, IV
92     o) MIPS V (SIMD vector stuff?)
93     o) MDMX (MIPS Digital Media Extension)
94     o) MIPS 3D
95     o) MIPS MT (Multi-thread stuff) (What's this?)
96     o) Warn about mis-used bit fields (ie bits that
97     should be all zeroes, warn about if they are not)!
98     Both for coprocessor registers and for instruction
99     opcodes.
100     o) the special2 stuff is a mess right now
101     o) warn and/or cause exceptions for unimplemented
102     instructions (depending on CPU type)
103     o) R2000/R3000:
104     x) R3000 "tri-byte stores". (What's this?)
105     o) R4000 and others:
106     x) watchhi/watchlo exceptions, and other exception
107     handling details
108     o) R10000 and others: (R12000, R14000 ?)
109     x) memory space, exceptions, ...
110     x) use cop0 framemask for tlb lookups
111     (http://techpubs.sgi.com/library/tpl/cgi-bin/getdoc.cgi/hdwr/bks/SGI_Developer/books/R10K_UM/sgi_html/t5.Ver.2.0.book_284.html)
112     o) Implement load delays? Warnings on interlocks.
113     o) Implement all coprocessor 0 bits / functions.
114     x) coproc 0 selectors! (R4000 ?)
115     o) R4300 (nintendo64, no mmu?), R5900 (playstation2, weird
116     TLB/cache? 128-bit GPRs, new instructions),
117     4K (note: NOT R4000), 5K (note: NOT R5000),
118     R6000 (ISA II), R8000
119     o) Multi-cpu stuff:
120 dpavlin 12 +) Interrupt routing (ie devices vs mainbus, or
121     connect each device to a fixed cpu)
122 dpavlin 2 +) SGI's NUMA architecture. Study
123     x) Linux sources
124     x) SGI's specs on NUMA address space
125     +) Ultrix? NetBSD doesn't do SMP on MIPS yet :-(
126     +) Own experiments with ycx2.
128     File/disk handling:
129     o) Better handling of tape files
131 dpavlin 12 Debugger:
132     o) Read function argument count and types from binaries? (ELF?)
133     o) Demangle C++ names.
135 dpavlin 2 Userland ABI emulation:
136     o) see src/useremul.c
138     Terminal based interactive debugger:
139     o) see src/debugger.c
141 dpavlin 6 Terminal/console stuff:
142     o) allow emulated serial ports to be connected to the outside
143     world in a more generic way, or even to other emulated
144     machines(!)
146 dpavlin 12 Regression tests. (Needs to be totally rewritten, the old framework
147     was removed because it was useless.)
148 dpavlin 2
149     Save state of the whole emulated machine, to be able to load it back
150     in later? (Memory, all device's states, all registers and
151     so on. Like taking a snapshot. (SimOS seems to do this,
152     according to its website.))
154     Better X-windows functionality:
155     o) CLEAN UP the ugly event code
156     o) Mouse clicks can be "missed" in the current system; this is
157     not good. They should be put on a stack of some kind.
158     o) More 2D and 3D framebuffer acceleration.
159     o) Non-resizable windows? Or choose scaledown depending
160     on size (and center the image, with a black border).
161     o) Different scaledown on different windows?
162     o) Switch scaledown during runtime? (Ala CTRL-ALT-plus/minus)
163     o) Keyboard and mouse events:
164     x) Do this for more machines than just DECstation
165     x) more X11 cursor keycodes
166     x) Keys like CTRL, ALT, SHIFT do not get through
167     by themselves (these are necessary for example
168     to change the font of an xterm in X in the
169     emulator)
170     o) Generalize the framebuffer stuff by moving _ALL_ X11
171     specific code to src/x11.c!
173     Statistics: (this could be interesting)
174     o) Save to file and show graphics. It should be possible to
175     run gxemul after a simulation to just show the graphics,
176     or convert to a .ppm or .tga or similar.
177     o) memory accesses (to measure cache efficiency and
178     page coloring efficiency)
179     o) nr of simultaneous ASIDs in use in the TLB, for MIPS
180     o) percentage of time spent in different "states", such as
181     running userland code, kernel code, or idling (for CPUs
182     that have such an instruction, or whenever the PC is
183     inside a specific idle-function (address range)).
184     Possible additional state (for example on R3000): caches
185     disabled.
186     o) position of read/write on (SCSI) disks

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