--- trunk/HISTORY 2007/10/08 16:18:27 10 +++ trunk/HISTORY 2007/10/08 16:19:56 24 @@ -1,4 +1,4 @@ -$Id: HISTORY,v 1.815 2005/06/27 23:04:35 debug Exp $ +$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $ Changelog for GXemul: --------------------- @@ -2035,3 +2035,771 @@ ============== RELEASE 0.3.4 ============== +20050628 Continuing the work on the ARM translation engine. end_of_page + works. Experimenting with load/store translation caches + (virtual -> physical -> host). +20050629 More ARM stuff (memory access translation cache, mostly). This + might break a lot of stuff elsewhere, probably some MIPS- + related translation things. +20050630 Many load/stores are now automatically generated and included + into cpu_arm_instr.c; 1024 functions in total (!). + Fixes based on feedback from Alec Voropay: only print 8 hex + digits instead of 16 in some cases when emulating 32-bit + machines; similar 8 vs 16 digit fix for breakpoint addresses; + 4Kc has 16 TLB entries, not 48; the MIPS config select1 + register is now printed with "reg ,0". + Also changing many other occurances of 16 vs 8 digit output. + Adding cache associativity fields to mips_cpu_types.h; updating + some other cache fields; making the output of + mips_cpu_dumpinfo() look nicer. + Generalizing the bintrans stuff for device accesses to also + work with the new translation system. (This might also break + some MIPS things.) + Adding multi-load/store instructions to the ARM disassembler + and the translator, and some optimizations of various kinds. +20050701 Adding a simple dev_disk (it can read/write sectors from + disk images). +20050712 Adding dev_ether (a simple ethernet send/receive device). + Debugger command "ninstrs" for toggling show_nr_of_instructions + during runtime. + Removing the framebuffer logo. +20050713 Continuing on dev_ether. + Adding a dummy cpu_alpha (again). +20050714 More work on cpu_alpha. +20050715 More work on cpu_alpha. Many instructions work, enough to run + a simple framebuffer fill test (similar to the ARM test). +20050716 More Alpha stuff. +20050717 Minor updates (Alpha stuff). +20050718 Minor updates (Alpha stuff). +20050719 Generalizing some Alpha instructions. +20050720 More Alpha-related updates. +20050721 Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha. +20050722 Alpha-related updates: userland stuff (Hello World using + write() compiled statically for FreeBSD/Alpha runs fine), and + more instructions are now implemented. +20050723 Fixing ldq_u and stq_u. + Adding more instructions (conditional moves, masks, extracts, + shifts). +20050724 More FreeBSD/Alpha userland stuff, and adding some more + instructions (inserts). +20050725 Continuing on the Alpha stuff. (Adding dummy ldt/stt.) + Adding a -A command line option to turn off alignment checks + in some cases (for translated code). + Trying to remove the old bintrans code which updated the pc + and nr_of_executed_instructions for every instruction. +20050726 Making another attempt att removing the pc/nr of instructions + code. This time it worked, huge performance increase for + artificial test code, but performance loss for real-world + code :-( so I'm scrapping that code for now. + Tiny performance increase on Alpha (by using ret instead of + jmp, to play nice with the Alpha's branch prediction) for the + old MIPS bintrans backend. +20050727 Various minor fixes and cleanups. +20050728 Switching from a 2-level virtual to host/physical translation + system for ARM emulation, to a 1-level translation. + Trying to switch from 2-level to 1-level for the MIPS bintrans + system as well (Alpha only, so far), but there is at least one + problem: caches and/or how they work with device mappings. +20050730 Doing the 2-level to 1-level conversion for the i386 backend. + The cache/device bug is still there for R2K/3K :( + Various other minor updates (Malta etc). + The mc146818 clock now updates the UIP bit in a way which works + better with Linux for at least sgimips and Malta emulation. + Beginning the work on refactoring the dyntrans system. +20050731 Continuing the dyntrans refactoring. + Fixing a small but serious host alignment bug in memory_rw. + Adding support for big-endian load/stores to the i386 bintrans + backend. + Another minor i386 bintrans backend update: stores from the + zero register are now one (or two) loads shorter. + The slt and sltu instructions were incorrectly implemented for + the i386 backend; only using them for 32-bit mode for now. +20050801 Continuing the dyntrans refactoring. + Cleanup of the ns16550 serial controller (removing unnecessary + code). + Bugfix (memory corruption bug) in dev_gt, and a patch/hack from + Alec Voropay for Linux/Malta. +20050802 More cleanup/refactoring of the dyntrans subsystem: adding + phys_page pointers to the lookup tables, for quick jumps + between translated pages. + Better fix for the ns16550 device (but still no real FIFO + functionality). + Converting cpu_ppc to the new dyntrans system. This means that + I will have to start from scratch with implementing each + instruction, and figure out how to implement dual 64/32-bit + modes etc. + Removing the URISC CPU family, because it was useless. +20050803 When selecting a machine type, the main type can now be omitted + if the subtype name is unique. (I.e. -E can be omitted.) + Fixing a dyntrans/device update bug. (Writes to offset 0 of + a device could sometimes go unnoticed.) + Adding an experimental "instruction combination" hack for + ARM for memset-like byte fill loops. +20050804 Minor progress on cpu_alpha and related things. + Finally fixing the MIPS dmult/dmultu bugs. + Fixing some minor TODOs. +20050805 Generalizing the 8259 PIC. It now also works with Cobalt + and evbmips emulation, in addition to the x86 hack. + Finally converting the ns16550 device to use devinit. + Continuing the work on the dyntrans system. Thinking about + how to add breakpoints. +20050806 More dyntrans updates. Breakpoints seem to work now. +20050807 Minor updates: cpu_alpha and related things; removing + dev_malta (as it isn't used any more). + Dyntrans: working on general "show trace tree" support. + The trace tree stuff now works with both the old MIPS code and + with newer dyntrans modes. :) + Continuing on Alpha-related stuff (trying to get *BSD to boot + a bit further, adding more instructions, etc). +20050808 Adding a dummy IA64 cpu family, and continuing the refactoring + of the dyntrans system. + Removing the regression test stuff, because it was more or + less useless. + Adding loadlinked/storeconditional type instructions to the + Alpha emulation. (Needed for Linux/alpha. Not very well tested + yet.) +20050809 The function call trace tree now prints a per-function nr of + arguments. (Semi-meaningless, since that data isn't read yet + from the ELFs; some hardcoded symbols such as memcpy() and + strlen() work fine, though.) + More dyntrans refactoring; taking out more of the things that + are common to all cpu families. +20050810 Working on adding support for "dual mode" for PPC dyntrans + (i.e. both 64-bit and 32-bit modes). + (Re)adding some simple PPC instructions. +20050811 Adding a dummy M68K cpu family. The dyntrans system isn't ready + for variable-length ISAs yet, so it's completely bogus so far. + Re-adding more PPC instructions. + Adding a hack to src/file.c which allows OpenBSD/mac68k a.out + kernels to be loaded. + Beginning to add PPC loads/stores. So far they only work in + 32-bit mode. +20050812 The configure file option "add_remote" now accepts symbolic + host names, in addition to numeric IPv4 addresses. + Re-adding more PPC instructions. +20050814 Continuing to port back more PPC instructions. + Found and fixed the cache/device write-update bug for 32-bit + MIPS bintrans. :-) + Triggered a really weird and annoying bug in Compaq's C + compiler; ccc sometimes outputs code which loads from an + address _before_ checking whether the pointer was NULL or not. + (I'm not sure how to handle this problem.) +20050815 Removing all of the old x86 instruction execution code; adding + a new (dummy) dyntrans module for x86. + Taking the first steps to extend the dyntrans system to support + variable-length instructions. + Slowly preparing for the next release. +20050816 Adding a dummy SPARC cpu module. + Minor updates (documentation etc) for the release. + +============== RELEASE 0.3.5 ============== + +20050816 Some success in decoding the way the SGI O2 PROM draws graphics + during bootup; lines/rectangles and bitmaps work, enough to + show the bootlogo etc. :-) + Adding more PPC instructions, and (dummy) BAT registers. +20050817 Updating the pckbc to support scancode type 3 keyboards + (required in order to interact with the SGI O2 PROM). + Adding more PPC instructions. +20050818 Adding more ARM instructions; general register forms. + Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy) + CATS machine mode (using SA110 as the default CPU). + Continuing on general dyntrans related stuff. +20050819 Register forms for ARM load/stores. Gaah! The Compaq C Compiler + bug is triggered for ARM loads as well, not just PPC :-( + Adding full support for ARM PC-relative load/stores, and load/ + stores where the PC register is the destination register. + Adding support for ARM a.out binaries. +20050820 Continuing to add more ARM instructions, and correcting some + bugs. Continuing on CATS emulation. + More work on the PPC stuff. +20050821 Minor PPC and ARM updates. Adding more machine types. +20050822 All ARM "data processing instructions" are now generated + automatically. +20050824 Beginning the work on the ARM system control coprocessor. + Adding support for ARM halfword load/stores, and signed loads. +20050825 Fixing an important bug related to the ARM condition codes. + OpenBSD/zaurus and NetBSD/netwinder now print some boot + messages. :) + Adding a dummy SH (Hitachi SuperH) cpu family. + Beginning to add some ARM virtual address translation. + MIPS bugfixes: unaligned PC now cause an ADEL exception (at + least for non-bintrans execution), and ADEL/ADES (not + TLBL/TLBS) are used if userland tries to access kernel space. + (Thanks to Joshua Wise for making me aware of these bugs.) +20050827 More work on the ARM emulation, and various other updates. +20050828 More ARM updates. + Finally taking the time to work on translation invalidation + (i.e. invalidating translated code mappings when memory is + written to). Hopefully this doesn't break anything. +20050829 Moving CPU related files from src/ to a new subdir, src/cpus/. + Moving PROM emulation stuff from src/ to src/promemul/. + Better debug instruction trace for ARM loads and stores. +20050830 Various ARM updates (correcting CMP flag calculation, etc). +20050831 PPC instruction updates. (Flag fixes, etc.) +20050901 Various minor PPC and ARM instruction emulation updates. + Minor OpenFirmware emulation updates. +20050903 Adding support for adding arbitrary ARM coprocessors (with + the i80321 I/O coprocessor as a first test). + Various other ARM and PPC updates. +20050904 Adding some SHcompact disassembly routines. +20050907 (Re)adding a dummy HPPA CPU module, and a dummy i960 module. +20050908 Began hacking on some Apple Partition Table support. +20050909 Adding support for loading Mach-O (Darwin PPC) binaries. +20050910 Fixing an ARM bug (Carry flag was incorrectly updated for some + data processing instructions); OpenBSD/cats and NetBSD/ + netwinder get quite a bit further now. + Applying a patch to dev_wdc, and a one-liner to dev_pcic, to + make them work better when emulating new versions of OpenBSD. + (Thanks to Alexander Yurchenko for the patches.) + Also doing some other minor updates to dev_wdc. (Some cleanup, + and finally converting to devinit, etc.) +20050912 IRIX doesn't have u_int64_t by default (noticed by Andreas + ); configure updated to reflect this. + Working on ARM register bank switching, CPSR vs SPSR issues, + and beginning the work on interrupt/exception support. +20050913 Various minor ARM updates (speeding up load/store multiple, + and fixing a ROR bug in R(); NetBSD/cats now boots as far as + OpenBSD/cats). +20050917 Adding a dummy Atmel AVR (8-bit) cpu family skeleton. +20050918 Various minor updates. +20050919 Symbols are now loaded from Mach-O executables. + Continuing the work on adding ARM exception support. +20050920 More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach + userland! :-) +20050921 Some more progress on ARM interrupt specifics. +20050923 Fixing linesize for VR4121 (patch by Yurchenko). Also fixing + linesizes/cachesizes for some other VR4xxx. + Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a + dummy Symphony Labs 83C553 bridge (for Netwinder), usable by + dev_footbridge. +20050924 Some PPC progress. +20050925 More PPC progress. +20050926 PPC progress (fixing some bugs etc); Darwin's kernel gets + slightly further than before. +20050928 Various updates: footbridge/ISA/pciide stuff, and finally + fixing the VGA text scroll-by-changing-the-base-offset bug. +20050930 Adding a dummy S3 ViRGE pci card for CATS emulation, which + both NetBSD and OpenBSD detects as VGA. + Continuing on Footbridge (timers, ISA interrupt stuff). +20051001 Continuing... there are still bugs, probably interrupt- + related. +20051002 More work on the Footbridge (interrupt stuff). +20051003 Various minor updates. (Trying to find the bug(s).) +20051004 Continuing on the ARM stuff. +20051005 More ARM-related fixes. +20051007 FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the + other was because of an error in the ARM manual (load multiple + with the S-bit set should _NOT_ load usermode registers, as the + manual says, but it should load saved registers, which may or + may not happen to be usermode registers). + NetBSD/cats and OpenBSD/cats seem to install fine now :-) + except for a minor bug at the end of the OpenBSD/cats install. + Updating the documentation, preparing for the next release. +20051008 Continuing with release testing and cleanup. + +============== RELEASE 0.3.6 ============== + +20051008 The bug was not because of faulty ARM documentation after all, + but it was related to those parts of the code. + Fixing the RTC (dev_mc146818) to work with CATS. +20051009 Rewriting the R() function; now there are 8192 automatically + generated smaller functions doing the same thing, but hopefully + faster. This also fixes some bugs which were triggered when + trying to compile GXemul inside itself. :-) + Adding a dummy dev_lpt. +20051010 Small hack to not update virtual translation tables if memory + accesses are done with the NO_EXCEPTION flag; a time reduction + of almost a factor 2 for a full NetBSD/cats install. :-) +20051011 Passing -A as the default boot arg for CATS (works fine with + OpenBSD/cats). + +============== RELEASE 0.3.6.1 ============== + +20051012 Fixing the VGA cursor offset bug, and speeding up framebuffer + redraws if character cells contain the same thing as during + the last redraw. +20051013 Adding a slow strd ARM instruction hack. +20051017 Minor updates: Adding a dummy i80321 Verde controller (for + XScale emulation), fixing the disassembly of the ARM "ldrd" + instruction, adding "support" for less-than-4KB pages for ARM + (by not adding them to translation tables). +20051020 Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints + some boot messages on an emulated Jornada 720. + Making dev_ram work better with dyntrans (speeds up some things + quite a bit). +20051021 Automatically generating some of the most common ARM load/store + multiple instructions. +20051022 Better statistics gathering for the ARM load/store multiple. + Various other dyntrans and device updates. +20051023 Various minor updates. +20051024 Continuing; minor device and dyntrans fine-tuning. Adding the + first "reasonable" instruction combination hacks for ARM (the + cores of NetBSD/cats' memset and memcpy). +20051025 Fixing a dyntrans-related bug in dev_vga. Also changing the + dyntrans low/high access notification to only be updated on + writes, not reads. Hopefully it will be enough. (dev_vga in + charcell mode now seems to work correctly with both reads and + writes.) + Experimenting with gathering dyntrans statistics (which parts + of emulated RAM that are actually executed), and adding + instruction combination hacks for cache cleaning and a part of + NetBSD's scanc() function. +20051026 Adding a bitmap for ARM emulation which indicates if a page is + (specifically) user accessible; loads and stores with the t- + flag set can now use the translation arrays, which results in + a measurable speedup. +20051027 Dyntrans updates; adding an extra bitmap array for 32-bit + emulation modes, speeding up the check whether a physical page + has any code translations or not (O(n) -> O(1)). Doing a + similar reduction of O(n) to O(1) by avoiding the scan through + the translation entries on a translation update (32-bit mode + only). + Various other minor hacks. +20051029 Quick release, without any testing at all. + +============== RELEASE 0.3.6.2 ============== + +20051031 Adding disassembly support for more ARM instructions (clz, + smul* etc), and adding a hack to support "new tiny" pages + for StrongARM. +20051101 Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD + 3.7 -> 3.8, and lots of testing). + Changing from 1-sector PIO mode 0 transfers to 128-sector PIO + mode 3 (in dev_wdc). + Various minor ARM dyntrans updates (pc-relative loads from + within the same page as the instruction are now treated as + constant "mov"). +20051102 Re-enabling instruction combinations (they were accidentally + disabled). + Dyntrans TLB entries are now overwritten using a round-robin + scheme instead of randomly. This increases performance. + Fixing a typo in file.c (thanks to Chuan-Hua Chang for + noticing it). + Experimenting with adding ATAPI support to dev_wdc (to make + emulated *BSD detect cdroms as cdroms, not harddisks). +20051104 Various minor updates. +20051105 Continuing on the ATAPI emulation. Seems to work well enough + for a NetBSD/cats installation, but not OpenBSD/cats. + Various other updates. +20051106 Modifying the -Y command line option to allow scaleup with + certain graphic controllers (only dev_vga so far), not just + scaledown. + Some minor dyntrans cleanups. +20051107 Beginning a cleanup up the PCI subsystem (removing the + read_register hack, etc). +20051108 Continuing the cleanup; splitting up some pci devices into a + normal autodev device and some separate pci glue code. +20051109 Continuing on the PCI bus stuff; all old pci_*.c have been + incorporated into normal devices and/or rewritten as glue code + only, adding a dummy Intel 82371AB PIIX4 for Malta (not really + tested yet). + Minor pckbc fix so that Linux doesn't complain. + Working on the DEC 21143 NIC (ethernet mac rom stuff mostly). + Various other minor fixes. +20051110 Some more ARM dyntrans fine-tuning (e.g. some instruction + combinations (cmps followed by conditional branch within the + same page) and special cases for DPIs with regform when the + shifter isn't used). +20051111 ARM dyntrans updates: O(n)->O(1) for just-mark-as-non- + writable in the generic pc_to_pointers function, and some other + minor hacks. + Merging Cobalt and evbmips (Malta) ISA interrupt handling, + and some minor fixes to allow Linux to accept harddisk irqs. +20051112 Minor device updates (pckbc, dec21143, lpt, ...), most + importantly fixing the ALI M1543/M5229 so that harddisk irqs + work with Linux/CATS. +20051113 Some more generalizations of the PCI subsystem. + Finally took the time to add a hack for SCSI CDROM TOCs; this + enables OpenBSD to use partition 'a' (as needed by the OpenBSD + installer), and Windows NT's installer to get a bit further. + Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs. + Continuing on the DEC 21143. +20051114 Minor ARM dyntrans tweaks; ARM cmps+branch optimization when + comparing with 0, and generalizing the xchg instr. comb. + Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}. +20051115 Continuing on various PPC things (BATs, other address trans- + lation things, various loads/stores, BeBox emulation, etc.). + Beginning to work on PPC interrupt/exception support. +20051116 Factoring out some code which initializes legacy ISA devices + from those machines that use them (bus_isa). + Continuing on PPC interrupt/exception support. +20051117 Minor Malta fixes: RTC year offset = 80, disabling a speed hack + which caused NetBSD to detect a too fast cpu, and adding a new + hack to make Linux detect a faster cpu. + Continuing on the Artesyn PM/PPC emulation mode. + Adding an Algor emulation skeleton (P4032 and P5064); + implementing some of the basics. + Continuing on PPC emulation in general; usage of unimplemented + SPRs is now easier to track, continuing on memory/exception + related issues, etc. +20051118 More work on PPC emulation (tgpr0..3, exception handling, + memory stuff, syscalls, etc.). +20051119 Changing the ARM dyntrans code to mostly use cpu->pc, and not + necessarily use arm reg 15. Seems to work. + Various PPC updates; continuing on the PReP emulation mode. +20051120 Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep + to detect the clock. +20051121 More cleanup of the PCI bus (memory and I/O bases, etc). + Continuing on various PPC things (decrementer and timebase, + WDCs on obio (on PReP) use irq 13, not 14/15). +20051122 Continuing on the CPC700 controller (interrupts etc) for PMPPC, + and on PPC stuff in general. + Finally! After some bug fixes to the virtual to physical addr + translation, NetBSD/{prep,pmppc} 2.1 reach userland and are + stable enough to be interacted with. + More PCI updates; reverse-endian device access for PowerPC etc. +20051123 Generalizing the IEEE floating point subsystem (moving it out + from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c). + Input via slave xterms was sometimes not really working; fixing + this for ns16550, and a warning message is now displayed if + multiple non-xterm consoles are active. + Adding some PPC floating point support, etc. + Various interrupt related updates (dev_wdc, _ns16550, _8259, + and the isa32 common code in machine.c). + NetBSD/prep can now be installed! :-) (Well, with some manual + commands necessary before running sysinst.) Updating the + documentation and various other things to reflect this. +20051124 Various minor documentation updates. + Continuing the work on the DEC 21143 NIC. +20051125 LOTS of work on the 21143. Both OpenBSD and NetBSD work fine + with it now, except that OpenBSD sometimes gives a time-out + warning. + Minor documentation updates. + +============== RELEASE 0.3.7 ============== + +20051126 Cobalt and PReP now work with the 21143 NIC. + Continuing on Alpha dyntrans things. + Fixing some more left-shift-by-24 to unsigned. +20051127 Working on OpenFirmware emulation; major cleanup/redesign. + Progress on MacPPC emulation: NetBSD detects two CPUs (when + running with -n 2), framebuffer output (for text) works. + Adding quick-hack Bandit PCI controller and "gc" interrupt + controller for MacPPC. +20051128 Changing from a Bandit to a Uni-North controller for macppc. + Continuing on OpenFirmware and MacPPC emulation in general + (obio controller, and wdc attached to the obio seems to work). +20051129 More work on MacPPC emulation (adding a dummy ADB controller). + Continuing the PCI bus cleanup (endianness and tag composition) + and rewriting all PCI controllers' access functions. +20051130 Various minor PPC dyntrans optimizations. + Manually inlining some parts of the framebuffer redraw routine. + Slowly beginning the conversion of the old MIPS emulation into + dyntrans (but this will take quite some time to get right). + Generalizing quick_pc_to_pointers. +20051201 Documentation update (David Muse has made available a kernel + which simplifies Debian/DECstation installation). + Continuing on the ADB bus controller. +20051202 Beginning a rewrite of the Zilog serial controller (dev_zs). +20051203 Continuing on the zs rewrite (now called dev_z8530); conversion + to devinit style. + Reworking some of the input-only vs output-only vs input-output + details of src/console.c, better warning messages, and adding + a debug dump. + Removing the concept of "device state"; it wasn't really used. + Changing some debug output (-vv should now be used to show all + details about devices and busses; not shown during normal + startup anymore). + Beginning on some SPARC instruction disassembly support. +20051204 Minor PPC updates (WALNUT skeleton stuff). + Continuing on the MIPS dyntrans rewrite. + More progress on the ADB controller (a keyboard is "detected" + by NetBSD and OpenBSD). + Downgrading OpenBSD/arc as a guest OS from "working" to + "almost working" in the documentation. + Progress on Algor emulation ("v3" PCI controller). +20051205 Minor updates. +20051207 Sorting devices according to address; this reduces complexity + of device lookups from O(n) to O(log n) in memory_rw (but no + real performance increase (yet) in experiments). +20051210 Beginning the work on native dyntrans backends (by making a + simple skeleton; so far only for Alpha hosts). +20051211 Some very minor SPARC updates. +20051215 Fixing a bug in the MIPS mul (note: not mult) instruction, + so it also works with non-64-bit emulation. (Thanks to Alec + Voropay for noticing the problem.) +20051216 More work on the fake/empty/simple/skeleton/whatever backend; + performance doesn't increase, so this isn't really worth it, + but it was probably worth it to prepare for a real backend + later. +20051219 More instr call statistics gathering and analysis stuff. +20051220 Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z} + to dyntrans. + memory_ppc.c syntax error fix (noticed by Peter Valchev). + Beginning to move out machines from src/machine.c into + individual files in src/machines (in a way similar to the + autodev system for devices). +20051222 Updating the documentation regarding NetBSD/pmax 3.0. +20051223 - " - NetBSD/cats 3.0. +20051225 - " - NetBSD/hpcmips 3.0. +20051226 Continuing on the machine registry redesign. + Adding support for ARM rrx (33-bit rotate). + Fixing some signed/unsigned issues (exposed by gcc -W). +20051227 Fixing the bug which prevented a NetBSD/prep 3.0 install kernel + from starting (triggered when an mtmsr was the last instruction + on a page). Unfortunately not enough to get the kernel to run + as well as the 2.1 kernels did. +20051230 Some dyntrans refactoring. +20051231 Continuing on the machine registry redesign. +20060101-10 Continuing... moving more machines. Moving MD interrupt stuff + from machine.c into a new src/machines/interrupts.c. +20060114 Adding various mvmeppc machine skeletons. +20060115 Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages + (for MVME1600) and reaches the root device prompt, but no + specific hardware devices are emulated yet. +20060116 Minor updates to the mvme1600 emulation mode; the Eagle PCI bus + seems to work without much modification, and a 21143 can be + detected, interrupts might work (but untested so far). + Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc. +20060121 Adding an aux control register for ARM. (A BIG thank you to + Olivier Houchard for tracking down this bug.) +20060122 Adding more ARM instructions (smulXY), and dev_iq80321_7seg. +20060124 Adding disassembly of more ARM instructions (mia*, mra/mar), + and some semi-bogus XScale and i80321 registers. +20060201-02 Various minor updates. Moving the last machines out of + machine.c. +20060204 Adding a -c command line option, for running debugger commands + before the simulation starts, but after all files have been + loaded. + Minor iq80321-related updates. +20060209 Minor hacks (DEVINIT macro, etc). + Preparing for the generalization of the 64-bit dyntrans address + translation subsystem. +20060216 Adding ARM ldrd (double-register load). +20060217 Continuing on various ARM-related stuff. +20060218 More progress on the ATA/wdc emulation for NetBSD/iq80321. + NetBSD/evbarm can now be installed :-) Updating the docs, etc. + Continuing on Algor emulation. + +============== RELEASE 0.3.8 ============== + +20060219 Various minor updates. Removing the old MIPS16 skeleton code, + because it will need to be rewritten for dyntrans anyway. +20060220-22 Removing the non-working dyntrans backend support. + Continuing on the 64-bit dyntrans virtual memory generalization. +20060223 More work on the 64-bit vm generalization. +20060225 Beginning on MIPS dyntrans load/store instructions. + Minor PPC updates (64-bit load/store, etc). + Fixes for the variable-instruction-length framework, some + minor AVR updates (a simple Hello World program works!). + Beginning on a skeleton for automatically generating documen- + tation (for devices etc.). +20060226 PPC updates (adding some more 64-bit instructions, etc). + AVR updates (more instructions). + FINALLY found and fixed the zs bug, making NetBSD/macppc + accept the serial console. +20060301 Adding more AVR instructions. +20060304 Continuing on AVR-related stuff. Beginning on a framework for + cycle-accurate device emulation. Adding an experimental "PAL + TV" device (just a dummy so far). +20060305 Adding more AVR instructions. + Adding a dummy epcom serial controller (for TS7200 emulation). +20060310 Removing the emul() command from configuration files, so only + net() and machine() are supported. + Minor progress on the MIPS dyntrans rewrite. +20060311 Continuing on the MIPS dyntrans rewrite (adding more + instructions, etc). +20060315 Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l], + beql, bnel, slti[u], various loads and stores). +20060316 Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely + used. + Adding more MIPS dyntrans instructions, and fixing bugs. +20060318 Implementing fast loads/stores for MIPS dyntrans (big/little + endian, 32-bit and 64-bit modes). +20060320 Making MIPS dyntrans the default configure option; use + "--enable-oldmips" to use the old bintrans system. + Adding MIPS dyntrans dmult[u]; minor updates. +20060322 Continuing... adding some more instructions. + Adding a simple skeleton for demangling C++ "_ZN" symbols. +20060323 Moving src/debugger.c into a new directory (src/debugger/). +20060324 Fixing the hack used to load PPC ELFs (useful for relocated + Linux/ppc kernels), and adding a dummy G3 machine mode. +20060325-26 Beginning to experiment with GDB remote serial protocol + connections; adding a -G command line option for selecting + which TCP port to listen to. +20060330 Beginning a major cleanup to replace things like "0x%016llx" + with more correct "0x%016"PRIx64, etc. + Continuing on the GDB remote serial protocol support. +20060331 More cleanup, and some minor GDB remote progress. +20060402 Adding a hack to the configure script, to allow compilation + on systems that lack PRIx64 etc. +20060406 Removing the temporary FreeBSD/arm hack in dev_ns16550.c and + replacing it with a better fix from Olivier Houchard. +20060407 A remote debugger (gdb or ddd) can now start and stop the + emulator using the GDB remote serial protocol, and registers + and memory can be read. MIPS only for now. +20060408 More GDB progress: single-stepping also works, and also adding + support for ARM, PowerPC, and Alpha targets. + Continuing on the delay-slot-across-page-boundary issue. +20060412 Minor update: beginning to add support for the SPARC target + to the remote GDB functionality. +20060414 Various MIPS updates: adding more instructions for dyntrans + (eret, add), and making some exceptions work. Fixing a bug + in dmult[u]. + Implementing the first SPARC instructions (sethi, or). +20060415 Adding "magic trap" instructions so that PROM calls can be + software emulated in MIPS dyntrans. + Adding more MIPS dyntrans instructions (ddiv, dadd) and + fixing another bug in dmult. +20060416 More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv, + rfi, an ugly hack for supporting R2000/R3000 style faked caches, + preliminary interrupt support, and various other updates and + bugfixes. +20060417 Adding more SPARC instructions (add, sub, sll[x], sra[x], + srl[x]), and useful SPARC header definitions. + Adding the first (trivial) x86/AMD64 dyntrans instructions (nop, + cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other + x86 updates related to variable instruction length stuff. + Adding unaligned loads/stores to the MIPS dyntrans mode (but + still using the pre-dyntrans (slow) imlementation). +20060419 Fixing a MIPS dyntrans exception-in-delay-slot bug. + Removing the old "show opcode statistics" functionality, since + it wasn't really useful and isn't implemented for dyntrans. + Single-stepping (or running with instruction trace) now looks + ok with dyntrans with delay-slot architectures. +20060420 Minor hacks (removing the -B command line option when compiled + for non-bintrans, and some other very minor updates). + Adding (slow) MIPS dyntrans load-linked/store-conditional. +20060422 Applying fixes for bugs discovered by Nils Weller's nwcc + (static DEC memmap => now per machine, and adding an extern + keyword in cpu_arm_instr.c). + Finally found one of the MIPS dyntrans bugs that I've been + looking for (copy/paste spelling error BIG vs LITTLE endian in + cpu_mips_instr_loadstore.c for 16-bit fast stores). + FINALLY found the major MIPS dyntrans bug: slti vs sltiu + signed/unsigned code in cpu_mips_instr.c. :-) + Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l], + ctc1, tlt[u], tge[u], tne, beginning on rdhwr). + NetBSD/hpcmips can now reach userland when using dyntrans :-) + Adding some more x86 dyntrans instructions. + Finally removed the old Alpha-specific virtual memory code, + and replaced it with the generic 64-bit version. + Beginning to add disassembly support for SPECIAL3 MIPS opcodes. +20060423 Continuing on the delay-slot-across-page-boundary issue; + adding an end_of_page2 ic slot (like I had planned before, but + had removed for some reason). + Adding a quick-and-dirty fallback to legacy coprocessor 1 + code (i.e. skipping dyntrans implementation for now). + NetBSD/hpcmips and NetBSD/pmax (when running on an emulated + R4400) can now be installed and run. :-) (Many bugs left + to fix, though.) + Adding more MIPS dyntrans instructions: madd[u], msub[u]. + Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode + maps somewhat (disassembly and dyntrans instruction decoding). +20060424 Adding an isa_revision field to mips_cpu_types.h, and making + sure that SPECIAL3 opcodes cause Reserved Instruction + exceptions on MIPS32/64 revisions lower than 2. + Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor' + instructions. +20060425 Removing the -m command line option ("run at most x + instructions") and -T ("single_step_on_bad_addr"), because + they never worked correctly with dyntrans anyway. + Freshening up the man page. +20060428 Adding more MIPS dyntrans instructions: bltzal[l], idle. + Enabling MIPS dyntrans compare interrupts. +20060429 FINALLY found the weird dyntrans bug, causing NetBSD etc. to + behave strangely: some floating point code (conditional + coprocessor branches) could not be reused from the old + non-dyntrans code. The "quick-and-dirty fallback" only appeared + to work. Fixing by implementing bc1* for MIPS dyntrans. + More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0. + Freshening up MIPS floating point disassembly appearance. +20060430 Continuing on C790/R5900/TX79 disassembly; implementing 128-bit + "por" and "pextlw". +20060504 Disabling -u (userland emulation) unless compiled as unstable + development version. + Beginning on freshening up the testmachine include files, + to make it easier to reuse those files (placing them in + src/include/testmachine/), and beginning on a set of "demos" + or "tutorials" for the testmachine functionality. + Minor updates to the MIPS GDB remote protocol stub. + Refreshing doc/experiments.html and gdb_remote.html. + Enabling Alpha emulation in the stable release configuration, + even though no guest OSes for Alpha can run yet. +20060505 Adding a generic 'settings' object, which will contain + references to settable variables (which will later be possible + to access using the debugger). +20060506 Updating dev_disk and corresponding demo/documentation (and + switching from SCSI to IDE disk types, so it actually works + with current test machines :-). +20060510 Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts, + so that fseeko() doesn't give a warning. + Updating the section about how dyntrans works (the "runnable + IR") in doc/intro.html. + Instruction updates (some x64=1 checks, some more R5900 + dyntrans stuff: better mul/mult separation from MIPS32/64, + adding ei and di). + Updating MIPS cpuregs.h to a newer one (from NetBSD). + Adding more MIPS dyntrans instructions: deret, ehb. +20060514 Adding disassembly and beginning implementation of SPARC wr + and wrpr instructions. +20060515 Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1 + machines. Adding the 32-bit "rd psr" instruction. +20060517 Disassembly support for the general SPARC rd instruction. + Partial implementation of the cmp (subcc) instruction. + Some other minor updates (making sure that R5900 processors + start up with the EIE bit enabled, otherwise Linux/playstation2 + receives no interrupts). +20060519 Minor MIPS updates/cleanups. +20060521 Moving the MeshCube machine into evbmips; this seems to work + reasonably well with a snapshot of a NetBSD MeshCube kernel. + Cleanup/fix of MIPS config0 register initialization. +20060529 Minor MIPS fixes, including a sign-extension fix to the + unaligned load/store code, which makes NetBSD/pmax on R3000 + work better with dyntrans. (Ultrix and Linux/DECstation still + don't work, though.) +20060530 Minor updates to the Alpha machine mode: adding an AlphaBook + mode, an LCA bus (forwarding accesses to an ISA bus), etc. +20060531 Applying a bugfix for the MIPS dyntrans sc[d] instruction from + Ondrej Palkovsky. (Many thanks.) +20060601 Minifix to allow ARM immediate msr instruction to not give + an error for some valid values. + More Alpha updates. +20060602 Some minor Alpha updates. +20060603 Adding the Alpha cmpbge instruction. NetBSD/alpha prints its + first boot messages :-) on an emulated Alphabook 1. +20060612 Minor updates; adding a dev_ether.h include file for the + testmachine ether device. Continuing the hunt for the dyntrans + bug which makes Linux and Ultrix on DECstation behave + strangely... FINALLY found it! It seems to be related to + invalidation of the translation cache, on tlbw{r,i}. There + also seems to be some remaining interrupt-related problems. +20060614 Correcting the implementation of ldc1/sdc1 for MIPS dyntrans + (so that it uses 16 32-bit registers if the FR bit in the + status register is not set). +20060616 REMOVING BINTRANS COMPLETELY! + Removing the old MIPS interpretation mode. + Removing the MFHILO_DELAY and instruction delay stuff, because + they wouldn't work with dyntrans anyway. +20060617 Some documentation updates (adding "NetBSD-archive" to some + URLs, and new Debian/DECstation installation screenshots). + Removing the "tracenull" and "enable-caches" configure options. + Improving MIPS dyntrans performance somewhat (only invalidate + translations if necessary, on writes to the entryhi register, + instead of doing it for all cop0 writes). +20060618 More cleanup after the removal of the old MIPS emulation. + Trying to fix the MIPS dyntrans performance bugs/bottlenecks; + only semi-successful so far (for R3000). +20060620 Minor update to allow clean compilation again on Tru64/Alpha. +20060622 MIPS cleanup and fixes (removing the pc_last stuff, which + doesn't make sense with dyntrans anyway, and fixing a cross- + page-delay-slot-with-exception case in end_of_page). + Removing the old max_random_cycles_per_chunk stuff, and the + concept of cycles vs instructions for MIPS emulation. + FINALLY found and fixed the bug which caused NetBSD/pmax + clocks to behave strangely (it was a load to the zero register, + which was treated as a NOP; now it is treated as a load to a + dummy scratch register). +20060623 Increasing the dyntrans chunk size back to + N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2. + Preparing for a quick release, even though there are known + bugs, and performance for non-R3000 MIPS emulation is very + poor. :-/ + Reverting to half the dyntrans chunk size again, because + NetBSD/cats seemed less stable with full size chunks. :( + NetBSD/sgimips 3.0 can now run :-) (With release 0.3.8, only + NetBSD/sgimips 2.1 worked, not 3.0.) + +============== RELEASE 0.4.0 ============== +