--- trunk/HISTORY 2007/10/08 16:18:27 10 +++ trunk/HISTORY 2007/10/08 16:18:51 14 @@ -1,4 +1,4 @@ -$Id: HISTORY,v 1.815 2005/06/27 23:04:35 debug Exp $ +$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $ Changelog for GXemul: --------------------- @@ -2035,3 +2035,265 @@ ============== RELEASE 0.3.4 ============== +20050628 Continuing the work on the ARM translation engine. end_of_page + works. Experimenting with load/store translation caches + (virtual -> physical -> host). +20050629 More ARM stuff (memory access translation cache, mostly). This + might break a lot of stuff elsewhere, probably some MIPS- + related translation things. +20050630 Many load/stores are now automatically generated and included + into cpu_arm_instr.c; 1024 functions in total (!). + Fixes based on feedback from Alec Voropay: only print 8 hex + digits instead of 16 in some cases when emulating 32-bit + machines; similar 8 vs 16 digit fix for breakpoint addresses; + 4Kc has 16 TLB entries, not 48; the MIPS config select1 + register is now printed with "reg ,0". + Also changing many other occurances of 16 vs 8 digit output. + Adding cache associativity fields to mips_cpu_types.h; updating + some other cache fields; making the output of + mips_cpu_dumpinfo() look nicer. + Generalizing the bintrans stuff for device accesses to also + work with the new translation system. (This might also break + some MIPS things.) + Adding multi-load/store instructions to the ARM disassembler + and the translator, and some optimizations of various kinds. +20050701 Adding a simple dev_disk (it can read/write sectors from + disk images). +20050712 Adding dev_ether (a simple ethernet send/receive device). + Debugger command "ninstrs" for toggling show_nr_of_instructions + during runtime. + Removing the framebuffer logo. +20050713 Continuing on dev_ether. + Adding a dummy cpu_alpha (again). +20050714 More work on cpu_alpha. +20050715 More work on cpu_alpha. Many instructions work, enough to run + a simple framebuffer fill test (similar to the ARM test). +20050716 More Alpha stuff. +20050717 Minor updates (Alpha stuff). +20050718 Minor updates (Alpha stuff). +20050719 Generalizing some Alpha instructions. +20050720 More Alpha-related updates. +20050721 Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha. +20050722 Alpha-related updates: userland stuff (Hello World using + write() compiled statically for FreeBSD/Alpha runs fine), and + more instructions are now implemented. +20050723 Fixing ldq_u and stq_u. + Adding more instructions (conditional moves, masks, extracts, + shifts). +20050724 More FreeBSD/Alpha userland stuff, and adding some more + instructions (inserts). +20050725 Continuing on the Alpha stuff. (Adding dummy ldt/stt.) + Adding a -A command line option to turn off alignment checks + in some cases (for translated code). + Trying to remove the old bintrans code which updated the pc + and nr_of_executed_instructions for every instruction. +20050726 Making another attempt att removing the pc/nr of instructions + code. This time it worked, huge performance increase for + artificial test code, but performance loss for real-world + code :-( so I'm scrapping that code for now. + Tiny performance increase on Alpha (by using ret instead of + jmp, to play nice with the Alpha's branch prediction) for the + old MIPS bintrans backend. +20050727 Various minor fixes and cleanups. +20050728 Switching from a 2-level virtual to host/physical translation + system for ARM emulation, to a 1-level translation. + Trying to switch from 2-level to 1-level for the MIPS bintrans + system as well (Alpha only, so far), but there is at least one + problem: caches and/or how they work with device mappings. +20050730 Doing the 2-level to 1-level conversion for the i386 backend. + The cache/device bug is still there for R2K/3K :( + Various other minor updates (Malta etc). + The mc146818 clock now updates the UIP bit in a way which works + better with Linux for at least sgimips and Malta emulation. + Beginning the work on refactoring the dyntrans system. +20050731 Continuing the dyntrans refactoring. + Fixing a small but serious host alignment bug in memory_rw. + Adding support for big-endian load/stores to the i386 bintrans + backend. + Another minor i386 bintrans backend update: stores from the + zero register are now one (or two) loads shorter. + The slt and sltu instructions were incorrectly implemented for + the i386 backend; only using them for 32-bit mode for now. +20050801 Continuing the dyntrans refactoring. + Cleanup of the ns16550 serial controller (removing unnecessary + code). + Bugfix (memory corruption bug) in dev_gt, and a patch/hack from + Alec Voropay for Linux/Malta. +20050802 More cleanup/refactoring of the dyntrans subsystem: adding + phys_page pointers to the lookup tables, for quick jumps + between translated pages. + Better fix for the ns16550 device (but still no real FIFO + functionality). + Converting cpu_ppc to the new dyntrans system. This means that + I will have to start from scratch with implementing each + instruction, and figure out how to implement dual 64/32-bit + modes etc. + Removing the URISC CPU family, because it was useless. +20050803 When selecting a machine type, the main type can now be omitted + if the subtype name is unique. (I.e. -E can be omitted.) + Fixing a dyntrans/device update bug. (Writes to offset 0 of + a device could sometimes go unnoticed.) + Adding an experimental "instruction combination" hack for + ARM for memset-like byte fill loops. +20050804 Minor progress on cpu_alpha and related things. + Finally fixing the MIPS dmult/dmultu bugs. + Fixing some minor TODOs. +20050805 Generalizing the 8259 PIC. It now also works with Cobalt + and evbmips emulation, in addition to the x86 hack. + Finally converting the ns16550 device to use devinit. + Continuing the work on the dyntrans system. Thinking about + how to add breakpoints. +20050806 More dyntrans updates. Breakpoints seem to work now. +20050807 Minor updates: cpu_alpha and related things; removing + dev_malta (as it isn't used any more). + Dyntrans: working on general "show trace tree" support. + The trace tree stuff now works with both the old MIPS code and + with newer dyntrans modes. :) + Continuing on Alpha-related stuff (trying to get *BSD to boot + a bit further, adding more instructions, etc). +20050808 Adding a dummy IA64 cpu family, and continuing the refactoring + of the dyntrans system. + Removing the regression test stuff, because it was more or + less useless. + Adding loadlinked/storeconditional type instructions to the + Alpha emulation. (Needed for Linux/alpha. Not very well tested + yet.) +20050809 The function call trace tree now prints a per-function nr of + arguments. (Semi-meaningless, since that data isn't read yet + from the ELFs; some hardcoded symbols such as memcpy() and + strlen() work fine, though.) + More dyntrans refactoring; taking out more of the things that + are common to all cpu families. +20050810 Working on adding support for "dual mode" for PPC dyntrans + (i.e. both 64-bit and 32-bit modes). + (Re)adding some simple PPC instructions. +20050811 Adding a dummy M68K cpu family. The dyntrans system isn't ready + for variable-length ISAs yet, so it's completely bogus so far. + Re-adding more PPC instructions. + Adding a hack to src/file.c which allows OpenBSD/mac68k a.out + kernels to be loaded. + Beginning to add PPC loads/stores. So far they only work in + 32-bit mode. +20050812 The configure file option "add_remote" now accepts symbolic + host names, in addition to numeric IPv4 addresses. + Re-adding more PPC instructions. +20050814 Continuing to port back more PPC instructions. + Found and fixed the cache/device write-update bug for 32-bit + MIPS bintrans. :-) + Triggered a really weird and annoying bug in Compaq's C + compiler; ccc sometimes outputs code which loads from an + address _before_ checking whether the pointer was NULL or not. + (I'm not sure how to handle this problem.) +20050815 Removing all of the old x86 instruction execution code; adding + a new (dummy) dyntrans module for x86. + Taking the first steps to extend the dyntrans system to support + variable-length instructions. + Slowly preparing for the next release. +20050816 Adding a dummy SPARC cpu module. + Minor updates (documentation etc) for the release. + +============== RELEASE 0.3.5 ============== + +20050816 Some success in decoding the way the SGI O2 PROM draws graphics + during bootup; lines/rectangles and bitmaps work, enough to + show the bootlogo etc. :-) + Adding more PPC instructions, and (dummy) BAT registers. +20050817 Updating the pckbc to support scancode type 3 keyboards + (required in order to interact with the SGI O2 PROM). + Adding more PPC instructions. +20050818 Adding more ARM instructions; general register forms. + Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy) + CATS machine mode (using SA110 as the default CPU). + Continuing on general dyntrans related stuff. +20050819 Register forms for ARM load/stores. Gaah! The Compaq C Compiler + bug is triggered for ARM loads as well, not just PPC :-( + Adding full support for ARM PC-relative load/stores, and load/ + stores where the PC register is the destination register. + Adding support for ARM a.out binaries. +20050820 Continuing to add more ARM instructions, and correcting some + bugs. Continuing on CATS emulation. + More work on the PPC stuff. +20050821 Minor PPC and ARM updates. Adding more machine types. +20050822 All ARM "data processing instructions" are now generated + automatically. +20050824 Beginning the work on the ARM system control coprocessor. + Adding support for ARM halfword load/stores, and signed loads. +20050825 Fixing an important bug related to the ARM condition codes. + OpenBSD/zaurus and NetBSD/netwinder now print some boot + messages. :) + Adding a dummy SH (Hitachi SuperH) cpu family. + Beginning to add some ARM virtual address translation. + MIPS bugfixes: unaligned PC now cause an ADEL exception (at + least for non-bintrans execution), and ADEL/ADES (not + TLBL/TLBS) are used if userland tries to access kernel space. + (Thanks to Joshua Wise for making me aware of these bugs.) +20050827 More work on the ARM emulation, and various other updates. +20050828 More ARM updates. + Finally taking the time to work on translation invalidation + (i.e. invalidating translated code mappings when memory is + written to). Hopefully this doesn't break anything. +20050829 Moving CPU related files from src/ to a new subdir, src/cpus/. + Moving PROM emulation stuff from src/ to src/promemul/. + Better debug instruction trace for ARM loads and stores. +20050830 Various ARM updates (correcting CMP flag calculation, etc). +20050831 PPC instruction updates. (Flag fixes, etc.) +20050901 Various minor PPC and ARM instruction emulation updates. + Minor OpenFirmware emulation updates. +20050903 Adding support for adding arbitrary ARM coprocessors (with + the i80321 I/O coprocessor as a first test). + Various other ARM and PPC updates. +20050904 Adding some SHcompact disassembly routines. +20050907 (Re)adding a dummy HPPA CPU module, and a dummy i960 module. +20050908 Began hacking on some Apple Partition Table support. +20050909 Adding support for loading Mach-O (Darwin PPC) binaries. +20050910 Fixing an ARM bug (Carry flag was incorrectly updated for some + data processing instructions); OpenBSD/cats and NetBSD/ + netwinder get quite a bit further now. + Applying a patch to dev_wdc, and a one-liner to dev_pcic, to + make them work better when emulating new versions of OpenBSD. + (Thanks to Alexander Yurchenko for the patches.) + Also doing some other minor updates to dev_wdc. (Some cleanup, + and finally converting to devinit, etc.) +20050912 IRIX doesn't have u_int64_t by default (noticed by Andreas + ); configure updated to reflect this. + Working on ARM register bank switching, CPSR vs SPSR issues, + and beginning the work on interrupt/exception support. +20050913 Various minor ARM updates (speeding up load/store multiple, + and fixing a ROR bug in R(); NetBSD/cats now boots as far as + OpenBSD/cats). +20050917 Adding a dummy Atmel AVR (8-bit) cpu family skeleton. +20050918 Various minor updates. +20050919 Symbols are now loaded from Mach-O executables. + Continuing the work on adding ARM exception support. +20050920 More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach + userland! :-) +20050921 Some more progress on ARM interrupt specifics. +20050923 Fixing linesize for VR4121 (patch by Yurchenko). Also fixing + linesizes/cachesizes for some other VR4xxx. + Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a + dummy Symphony Labs 83C553 bridge (for Netwinder), usable by + dev_footbridge. +20050924 Some PPC progress. +20050925 More PPC progress. +20050926 PPC progress (fixing some bugs etc); Darwin's kernel gets + slightly further than before. +20050928 Various updates: footbridge/ISA/pciide stuff, and finally + fixing the VGA text scroll-by-changing-the-base-offset bug. +20050930 Adding a dummy S3 ViRGE pci card for CATS emulation, which + both NetBSD and OpenBSD detects as VGA. + Continuing on Footbridge (timers, ISA interrupt stuff). +20051001 Continuing... there are still bugs, probably interrupt- + related. +20051002 More work on the Footbridge (interrupt stuff). +20051003 Various minor updates. (Trying to find the bug(s).) +20051004 Continuing on the ARM stuff. +20051005 More ARM-related fixes. +20051007 FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the + other was because of an error in the ARM manual (load multiple + with the S-bit set should _NOT_ load usermode registers, as the + manual says, but it should load saved registers, which may or + may not happen to be usermode registers). + NetBSD/cats and OpenBSD/cats seem to install fine now :-) + except for a minor bug at the end of the OpenBSD/cats install. + Updating the documentation, preparing for the next release. +20051008 Continuing with release testing and cleanup.