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dpavlin |
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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* Template code for MTS. |
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*/ |
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dpavlin |
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#define MTS_ENTRY MTS_NAME(entry_t) |
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#define MTS_CACHE(cpu) ( cpu->mts_u. MTS_NAME(cache) ) |
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dpavlin |
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/* Forward declarations */ |
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static forced_inline void *MTS_PROTO(access)(cpu_mips_t *cpu,m_uint64_t vaddr, |
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u_int op_code,u_int op_size, |
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u_int op_type,m_uint64_t *data, |
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u_int *exc); |
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static fastcall int MTS_PROTO(translate)(cpu_mips_t *cpu,m_uint64_t vaddr, |
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m_uint32_t *phys_page); |
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/* Initialize the MTS subsystem for the specified CPU */ |
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int MTS_PROTO(init)(cpu_mips_t *cpu) |
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{ |
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size_t len; |
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/* Initialize the cache entries to 0 (empty) */ |
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dpavlin |
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len = MTS_NAME_UP(HASH_SIZE) * sizeof(MTS_ENTRY); |
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if (!(MTS_CACHE(cpu) = malloc(len))) |
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dpavlin |
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return(-1); |
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dpavlin |
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memset(MTS_CACHE(cpu),0xFF,len); |
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dpavlin |
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cpu->mts_lookups = 0; |
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cpu->mts_misses = 0; |
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return(0); |
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} |
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/* Free memory used by MTS */ |
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void MTS_PROTO(shutdown)(cpu_mips_t *cpu) |
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{ |
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/* Free the cache itself */ |
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dpavlin |
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free(MTS_CACHE(cpu)); |
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MTS_CACHE(cpu) = NULL; |
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dpavlin |
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} |
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/* Show MTS detailed information (debugging only!) */ |
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dpavlin |
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void MTS_PROTO(show_stats)(cpu_gen_t *gen_cpu) |
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dpavlin |
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{ |
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dpavlin |
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cpu_mips_t *cpu = CPU_MIPS64(gen_cpu); |
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dpavlin |
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#if DEBUG_MTS_MAP_VIRT |
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MTS_ENTRY *entry; |
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dpavlin |
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u_int i,count; |
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dpavlin |
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#endif |
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dpavlin |
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printf("\nCPU%u: MTS%d statistics:\n",cpu->gen->id,MTS_ADDR_SIZE); |
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dpavlin |
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#if DEBUG_MTS_MAP_VIRT |
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/* Valid hash entries */ |
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dpavlin |
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for(count=0,i=0;i<MTS_NAME_UP(HASH_SIZE);i++) { |
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entry = &(MTS_CACHE(cpu)[i]); |
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if (!(entry->gvpa & MTS_INV_ENTRY_MASK)) { |
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printf(" %4u: vaddr=0x%8.8llx, paddr=0x%8.8llx, hpa=%p\n", |
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i,(m_uint64_t)entry->gvpa,(m_uint64_t)entry->gppa, |
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(void *)entry->hpa); |
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dpavlin |
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count++; |
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} |
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} |
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dpavlin |
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printf(" %u/%u valid hash entries.\n",count,MTS_NAME_UP(HASH_SIZE)); |
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dpavlin |
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#endif |
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dpavlin |
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printf(" Total lookups: %llu, misses: %llu, efficiency: %g%%\n", |
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cpu->mts_lookups, cpu->mts_misses, |
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100 - ((double)(cpu->mts_misses*100)/ |
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(double)cpu->mts_lookups)); |
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dpavlin |
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} |
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/* Invalidate the complete MTS cache */ |
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void MTS_PROTO(invalidate_cache)(cpu_mips_t *cpu) |
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{ |
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size_t len; |
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dpavlin |
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len = MTS_NAME_UP(HASH_SIZE) * sizeof(MTS_ENTRY); |
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memset(MTS_CACHE(cpu),0xFF,len); |
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dpavlin |
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} |
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/* Invalidate partially the MTS cache, given a TLB entry index */ |
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void MTS_PROTO(invalidate_tlb_entry)(cpu_mips_t *cpu,u_int tlb_index) |
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{ |
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dpavlin |
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MTS_PROTO(invalidate_cache)(cpu); |
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dpavlin |
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} |
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/* |
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* MTS mapping. |
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* |
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* It is NOT inlined since it triggers a GCC bug on my config (x86, GCC 3.3.5) |
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*/ |
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dpavlin |
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static no_inline MTS_ENTRY * |
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MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_type,mts_map_t *map, |
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MTS_ENTRY *entry,MTS_ENTRY *alt_entry) |
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dpavlin |
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{ |
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struct vdevice *dev; |
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dpavlin |
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m_uint32_t offset; |
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m_iptr_t host_ptr; |
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int cow; |
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dpavlin |
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dpavlin |
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if (!(dev = dev_lookup(cpu->vm,map->paddr,map->cached))) |
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return NULL; |
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dpavlin |
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dpavlin |
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if (dev->flags & VDEVICE_FLAG_SPARSE) { |
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host_ptr = dev_sparse_get_host_addr(cpu->vm,dev,map->paddr,op_type,&cow); |
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dpavlin |
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dpavlin |
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entry->gvpa = map->vaddr; |
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entry->gppa = map->paddr; |
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entry->hpa = host_ptr; |
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entry->flags = (cow) ? MTS_FLAG_COW : 0; |
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return entry; |
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dpavlin |
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} |
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dpavlin |
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if (!dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP)) { |
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offset = map->paddr - dev->phys_addr; |
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dpavlin |
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dpavlin |
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alt_entry->gvpa = map->vaddr; |
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alt_entry->gppa = map->paddr; |
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alt_entry->hpa = (dev->id << MTS_DEVID_SHIFT) + offset; |
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alt_entry->flags = MTS_FLAG_DEV; |
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return alt_entry; |
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} |
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entry->gvpa = map->vaddr; |
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entry->gppa = map->paddr; |
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entry->hpa = dev->host_addr + (map->paddr - dev->phys_addr); |
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entry->flags = 0; |
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return entry; |
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dpavlin |
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} |
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/* MTS lookup */ |
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static void *MTS_PROTO(lookup)(cpu_mips_t *cpu,m_uint64_t vaddr) |
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{ |
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m_uint64_t data; |
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u_int exc; |
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return(MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ, |
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&data,&exc)); |
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} |
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/* === MIPS Memory Operations ============================================= */ |
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/* LB: Load Byte */ |
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fastcall u_int MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LB,1,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr; |
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if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,8); |
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return(exc); |
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} |
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/* LBU: Load Byte Unsigned */ |
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fastcall u_int MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LBU,1,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr; |
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if (likely(!exc)) cpu->gpr[reg] = data & 0xff; |
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return(exc); |
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} |
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/* LH: Load Half-Word */ |
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fastcall u_int MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LH,2,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr); |
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if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,16); |
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return(exc); |
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} |
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/* LHU: Load Half-Word Unsigned */ |
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fastcall u_int MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LHU,2,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr); |
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if (likely(!exc)) cpu->gpr[reg] = data & 0xffff; |
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return(exc); |
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} |
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/* LW: Load Word */ |
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fastcall u_int MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LW,4,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr); |
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if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,32); |
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return(exc); |
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} |
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/* LWU: Load Word Unsigned */ |
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fastcall u_int MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LWU,4,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr); |
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if (likely(!exc)) cpu->gpr[reg] = data & 0xffffffff; |
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return(exc); |
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} |
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/* LD: Load Double-Word */ |
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fastcall u_int MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LD,8,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr); |
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if (likely(!exc)) cpu->gpr[reg] = data; |
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return(exc); |
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} |
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/* SB: Store Byte */ |
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fastcall u_int MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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data = cpu->gpr[reg] & 0xff; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SB,1,MTS_WRITE,&data,&exc); |
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if (likely(haddr != NULL)) *(m_uint8_t *)haddr = data; |
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return(exc); |
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} |
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/* SH: Store Half-Word */ |
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fastcall u_int MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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data = cpu->gpr[reg] & 0xffff; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SH,2,MTS_WRITE,&data,&exc); |
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if (likely(haddr != NULL)) *(m_uint16_t *)haddr = htovm16(data); |
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return(exc); |
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} |
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/* SW: Store Word */ |
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fastcall u_int MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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data = cpu->gpr[reg] & 0xffffffff; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SW,4,MTS_WRITE,&data,&exc); |
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if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
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return(exc); |
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} |
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/* SD: Store Double-Word */ |
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fastcall u_int MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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data = cpu->gpr[reg]; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SD,8,MTS_WRITE,&data,&exc); |
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if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
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return(exc); |
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} |
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/* LDC1: Load Double-Word To Coprocessor 1 */ |
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fastcall u_int MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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u_int exc; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LDC1,8,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr); |
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if (likely(!exc)) cpu->fpu.reg[reg] = data; |
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return(exc); |
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} |
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/* LWL: Load Word Left */ |
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fastcall u_int MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t r_mask,naddr; |
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m_uint64_t data; |
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u_int m_shift; |
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void *haddr; |
311 |
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u_int exc; |
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naddr = vaddr & ~(0x03); |
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haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWL,4,MTS_READ,&data,&exc); |
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if (likely(haddr != NULL)) |
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data = vmtoh32(*(m_uint32_t *)haddr); |
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if (likely(!exc)) { |
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m_shift = (vaddr & 0x03) << 3; |
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r_mask = (1ULL << m_shift) - 1; |
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data <<= m_shift; |
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cpu->gpr[reg] &= r_mask; |
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cpu->gpr[reg] |= data; |
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cpu->gpr[reg] = sign_extend(cpu->gpr[reg],32); |
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} |
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return(exc); |
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} |
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/* LWR: Load Word Right */ |
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fastcall u_int MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
334 |
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m_uint64_t r_mask,naddr; |
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m_uint64_t data; |
336 |
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u_int m_shift; |
337 |
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void *haddr; |
338 |
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u_int exc; |
339 |
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340 |
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naddr = vaddr & ~(0x03); |
341 |
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haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWR,4,MTS_READ,&data,&exc); |
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343 |
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if (likely(haddr != NULL)) |
344 |
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data = vmtoh32(*(m_uint32_t *)haddr); |
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346 |
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if (likely(!exc)) { |
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|
|
m_shift = ((vaddr & 0x03) + 1) << 3; |
348 |
|
|
r_mask = (1ULL << m_shift) - 1; |
349 |
|
|
|
350 |
|
|
data = sign_extend(data >> (32 - m_shift),32); |
351 |
|
|
r_mask = sign_extend(r_mask,32); |
352 |
|
|
|
353 |
|
|
cpu->gpr[reg] &= ~r_mask; |
354 |
|
|
cpu->gpr[reg] |= data; |
355 |
|
|
} |
356 |
|
|
return(exc); |
357 |
|
|
} |
358 |
|
|
|
359 |
|
|
/* LDL: Load Double-Word Left */ |
360 |
|
|
fastcall u_int MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
361 |
|
|
{ |
362 |
|
|
m_uint64_t r_mask,naddr; |
363 |
|
|
m_uint64_t data; |
364 |
|
|
u_int m_shift; |
365 |
|
|
void *haddr; |
366 |
|
|
u_int exc; |
367 |
|
|
|
368 |
|
|
naddr = vaddr & ~(0x07); |
369 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDL,8,MTS_READ,&data,&exc); |
370 |
|
|
|
371 |
|
|
if (likely(haddr != NULL)) |
372 |
|
|
data = vmtoh64(*(m_uint64_t *)haddr); |
373 |
|
|
|
374 |
|
|
if (likely(!exc)) { |
375 |
|
|
m_shift = (vaddr & 0x07) << 3; |
376 |
|
|
r_mask = (1ULL << m_shift) - 1; |
377 |
|
|
data <<= m_shift; |
378 |
|
|
|
379 |
|
|
cpu->gpr[reg] &= r_mask; |
380 |
|
|
cpu->gpr[reg] |= data; |
381 |
|
|
} |
382 |
|
|
return(exc); |
383 |
|
|
} |
384 |
|
|
|
385 |
|
|
/* LDR: Load Double-Word Right */ |
386 |
|
|
fastcall u_int MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
387 |
|
|
{ |
388 |
|
|
m_uint64_t r_mask,naddr; |
389 |
|
|
m_uint64_t data; |
390 |
|
|
u_int m_shift; |
391 |
|
|
void *haddr; |
392 |
|
|
u_int exc; |
393 |
|
|
|
394 |
|
|
naddr = vaddr & ~(0x07); |
395 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDR,8,MTS_READ,&data,&exc); |
396 |
|
|
|
397 |
|
|
if (likely(haddr != NULL)) |
398 |
|
|
data = vmtoh64(*(m_uint64_t *)haddr); |
399 |
|
|
|
400 |
|
|
if (likely(!exc)) { |
401 |
|
|
m_shift = ((vaddr & 0x07) + 1) << 3; |
402 |
|
|
r_mask = (1ULL << m_shift) - 1; |
403 |
|
|
data >>= (64 - m_shift); |
404 |
|
|
|
405 |
|
|
cpu->gpr[reg] &= ~r_mask; |
406 |
|
|
cpu->gpr[reg] |= data; |
407 |
|
|
} |
408 |
|
|
return(exc); |
409 |
|
|
} |
410 |
|
|
|
411 |
|
|
/* SWL: Store Word Left */ |
412 |
|
|
fastcall u_int MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
413 |
|
|
{ |
414 |
|
|
m_uint64_t d_mask,naddr; |
415 |
|
|
m_uint64_t data; |
416 |
|
|
u_int r_shift; |
417 |
|
|
void *haddr; |
418 |
|
|
u_int exc; |
419 |
|
|
|
420 |
|
|
naddr = vaddr & ~(0x03ULL); |
421 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_READ,&data,&exc); |
422 |
|
|
if (unlikely(exc)) return(exc); |
423 |
|
|
|
424 |
|
|
if (likely(haddr != NULL)) |
425 |
|
|
data = vmtoh32(*(m_uint32_t *)haddr); |
426 |
|
|
|
427 |
|
|
r_shift = (vaddr & 0x03) << 3; |
428 |
|
|
d_mask = 0xffffffff >> r_shift; |
429 |
|
|
|
430 |
|
|
data &= ~d_mask; |
431 |
|
|
data |= (cpu->gpr[reg] & 0xffffffff) >> r_shift; |
432 |
|
|
|
433 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_WRITE,&data,&exc); |
434 |
|
|
if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
435 |
|
|
return(exc); |
436 |
|
|
} |
437 |
|
|
|
438 |
|
|
/* SWR: Store Word Right */ |
439 |
|
|
fastcall u_int MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
440 |
|
|
{ |
441 |
|
|
m_uint64_t d_mask,naddr; |
442 |
|
|
m_uint64_t data; |
443 |
|
|
u_int r_shift; |
444 |
|
|
void *haddr; |
445 |
|
|
u_int exc; |
446 |
|
|
|
447 |
|
|
naddr = vaddr & ~(0x03); |
448 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_READ,&data,&exc); |
449 |
|
|
if (unlikely(exc)) return(exc); |
450 |
|
|
|
451 |
|
|
if (likely(haddr != NULL)) |
452 |
|
|
data = vmtoh32(*(m_uint32_t *)haddr); |
453 |
|
|
|
454 |
|
|
r_shift = ((vaddr & 0x03) + 1) << 3; |
455 |
|
|
d_mask = 0xffffffff >> r_shift; |
456 |
|
|
|
457 |
|
|
data &= d_mask; |
458 |
|
|
data |= (cpu->gpr[reg] << (32 - r_shift)) & 0xffffffff; |
459 |
|
|
|
460 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_WRITE,&data,&exc); |
461 |
|
|
if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
462 |
|
|
return(exc); |
463 |
|
|
} |
464 |
|
|
|
465 |
|
|
/* SDL: Store Double-Word Left */ |
466 |
|
|
fastcall u_int MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
467 |
|
|
{ |
468 |
|
|
m_uint64_t d_mask,naddr; |
469 |
|
|
m_uint64_t data; |
470 |
|
|
u_int r_shift; |
471 |
|
|
void *haddr; |
472 |
|
|
u_int exc; |
473 |
|
|
|
474 |
|
|
naddr = vaddr & ~(0x07); |
475 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_READ,&data,&exc); |
476 |
|
|
if (unlikely(exc)) return(exc); |
477 |
|
|
|
478 |
|
|
if (likely(haddr != NULL)) |
479 |
|
|
data = vmtoh64(*(m_uint64_t *)haddr); |
480 |
|
|
|
481 |
|
|
r_shift = (vaddr & 0x07) << 3; |
482 |
|
|
d_mask = 0xffffffffffffffffULL >> r_shift; |
483 |
|
|
|
484 |
|
|
data &= ~d_mask; |
485 |
|
|
data |= cpu->gpr[reg] >> r_shift; |
486 |
|
|
|
487 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_WRITE,&data,&exc); |
488 |
|
|
if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
489 |
|
|
return(exc); |
490 |
|
|
} |
491 |
|
|
|
492 |
|
|
/* SDR: Store Double-Word Right */ |
493 |
|
|
fastcall u_int MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
494 |
|
|
{ |
495 |
|
|
m_uint64_t d_mask,naddr; |
496 |
|
|
m_uint64_t data; |
497 |
|
|
u_int r_shift; |
498 |
|
|
void *haddr; |
499 |
|
|
u_int exc; |
500 |
|
|
|
501 |
|
|
naddr = vaddr & ~(0x07); |
502 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_READ,&data,&exc); |
503 |
|
|
if (unlikely(exc)) return(exc); |
504 |
|
|
|
505 |
|
|
if (likely(haddr != NULL)) |
506 |
|
|
data = vmtoh64(*(m_uint64_t *)haddr); |
507 |
|
|
|
508 |
|
|
r_shift = ((vaddr & 0x07) + 1) << 3; |
509 |
|
|
d_mask = 0xffffffffffffffffULL >> r_shift; |
510 |
|
|
|
511 |
|
|
data &= d_mask; |
512 |
|
|
data |= cpu->gpr[reg] << (64 - r_shift); |
513 |
|
|
|
514 |
|
|
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_WRITE,&data,&exc); |
515 |
|
|
if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
516 |
|
|
return(exc); |
517 |
|
|
} |
518 |
|
|
|
519 |
|
|
/* LL: Load Linked */ |
520 |
|
|
fastcall u_int MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
521 |
|
|
{ |
522 |
|
|
m_uint64_t data; |
523 |
|
|
void *haddr; |
524 |
|
|
u_int exc; |
525 |
|
|
|
526 |
|
|
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LL,4,MTS_READ,&data,&exc); |
527 |
|
|
if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr); |
528 |
|
|
|
529 |
|
|
if (likely(!exc)) { |
530 |
|
|
cpu->gpr[reg] = sign_extend(data,32); |
531 |
|
|
cpu->ll_bit = 1; |
532 |
|
|
} |
533 |
|
|
|
534 |
|
|
return(exc); |
535 |
|
|
} |
536 |
|
|
|
537 |
|
|
/* SC: Store Conditional */ |
538 |
|
|
fastcall u_int MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
539 |
|
|
{ |
540 |
|
|
m_uint64_t data; |
541 |
|
|
void *haddr; |
542 |
|
|
u_int exc = 0; |
543 |
|
|
|
544 |
|
|
if (cpu->ll_bit) { |
545 |
|
|
data = cpu->gpr[reg] & 0xffffffff; |
546 |
|
|
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SC,4,MTS_WRITE, |
547 |
|
|
&data,&exc); |
548 |
|
|
if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
549 |
|
|
} |
550 |
|
|
|
551 |
|
|
if (likely(!exc)) |
552 |
|
|
cpu->gpr[reg] = cpu->ll_bit; |
553 |
|
|
return(exc); |
554 |
|
|
} |
555 |
|
|
|
556 |
|
|
/* SDC1: Store Double-Word from Coprocessor 1 */ |
557 |
|
|
fastcall u_int MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
558 |
|
|
{ |
559 |
|
|
m_uint64_t data; |
560 |
|
|
void *haddr; |
561 |
|
|
u_int exc; |
562 |
|
|
|
563 |
|
|
data = cpu->fpu.reg[reg]; |
564 |
|
|
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE, |
565 |
|
|
&data,&exc); |
566 |
|
|
if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
567 |
|
|
return(exc); |
568 |
|
|
} |
569 |
|
|
|
570 |
|
|
/* CACHE: Cache operation */ |
571 |
|
|
fastcall u_int MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op) |
572 |
|
|
{ |
573 |
dpavlin |
7 |
mips64_jit_tcb_t *block; |
574 |
dpavlin |
4 |
m_uint32_t phys_page; |
575 |
|
|
|
576 |
|
|
#if DEBUG_CACHE |
577 |
dpavlin |
7 |
cpu_log(cpu->gen, |
578 |
|
|
"MTS","CACHE: PC=0x%llx, vaddr=0x%llx, cache=%u, code=%u\n", |
579 |
dpavlin |
4 |
cpu->pc, vaddr, op & 0x3, op >> 2); |
580 |
|
|
#endif |
581 |
|
|
|
582 |
|
|
if (!cpu->translate(cpu,vaddr,&phys_page)) { |
583 |
|
|
if ((phys_page < 1048576) && cpu->exec_phys_map) { |
584 |
|
|
block = cpu->exec_phys_map[phys_page]; |
585 |
|
|
|
586 |
|
|
if (block) { |
587 |
|
|
if ((cpu->pc < block->start_pc) || |
588 |
|
|
((cpu->pc - block->start_pc) >= MIPS_MIN_PAGE_SIZE)) |
589 |
|
|
{ |
590 |
|
|
#if DEBUG_CACHE |
591 |
dpavlin |
7 |
cpu_log(cpu->gen,"MTS", |
592 |
dpavlin |
4 |
"CACHE: removing compiled page at 0x%llx, pc=0x%llx\n", |
593 |
|
|
block->start_pc,cpu->pc); |
594 |
|
|
#endif |
595 |
|
|
cpu->exec_phys_map[phys_page] = NULL; |
596 |
dpavlin |
7 |
mips64_jit_tcb_free(cpu,block,TRUE); |
597 |
dpavlin |
4 |
} |
598 |
|
|
else |
599 |
|
|
{ |
600 |
|
|
#if DEBUG_CACHE |
601 |
dpavlin |
7 |
cpu_log(cpu->gen,"MTS", |
602 |
dpavlin |
4 |
"CACHE: trying to remove page 0x%llx with pc=0x%llx\n", |
603 |
|
|
block->start_pc,cpu->pc); |
604 |
|
|
#endif |
605 |
|
|
} |
606 |
|
|
} |
607 |
|
|
} |
608 |
|
|
} |
609 |
|
|
|
610 |
|
|
return(0); |
611 |
|
|
} |
612 |
|
|
|
613 |
|
|
/* === MTS Cache Management ============================================= */ |
614 |
|
|
|
615 |
|
|
/* MTS map/unmap/rebuild "API" functions */ |
616 |
|
|
void MTS_PROTO(api_map)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint64_t paddr, |
617 |
|
|
m_uint32_t len,int cache_access,int tlb_index) |
618 |
|
|
{ |
619 |
|
|
/* nothing to do, the cache will be filled on-the-fly */ |
620 |
|
|
} |
621 |
|
|
|
622 |
|
|
void MTS_PROTO(api_unmap)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t len, |
623 |
|
|
m_uint32_t val,int tlb_index) |
624 |
|
|
{ |
625 |
|
|
/* Invalidate the TLB entry or the full cache if no index is specified */ |
626 |
|
|
if (tlb_index != -1) |
627 |
|
|
MTS_PROTO(invalidate_tlb_entry)(cpu,tlb_index); |
628 |
|
|
else |
629 |
|
|
MTS_PROTO(invalidate_cache)(cpu); |
630 |
|
|
} |
631 |
|
|
|
632 |
dpavlin |
7 |
void MTS_PROTO(api_rebuild)(cpu_gen_t *cpu) |
633 |
dpavlin |
4 |
{ |
634 |
dpavlin |
7 |
MTS_PROTO(invalidate_cache)(CPU_MIPS64(cpu)); |
635 |
dpavlin |
4 |
} |
636 |
|
|
|
637 |
|
|
/* ======================================================================== */ |
638 |
|
|
|
639 |
|
|
/* Initialize memory access vectors */ |
640 |
|
|
void MTS_PROTO(init_memop_vectors)(cpu_mips_t *cpu) |
641 |
|
|
{ |
642 |
|
|
/* XXX TODO: |
643 |
|
|
* - LD/SD forbidden in Supervisor/User modes with 32-bit addresses. |
644 |
|
|
*/ |
645 |
|
|
|
646 |
|
|
cpu->addr_mode = MTS_ADDR_SIZE; |
647 |
|
|
|
648 |
|
|
/* API vectors */ |
649 |
|
|
cpu->mts_map = MTS_PROTO(api_map); |
650 |
|
|
cpu->mts_unmap = MTS_PROTO(api_unmap); |
651 |
|
|
|
652 |
dpavlin |
7 |
/* Memory lookup operation */ |
653 |
dpavlin |
4 |
cpu->mem_op_lookup = MTS_PROTO(lookup); |
654 |
|
|
|
655 |
|
|
/* Translation operation */ |
656 |
|
|
cpu->translate = MTS_PROTO(translate); |
657 |
|
|
|
658 |
|
|
/* Shutdown operation */ |
659 |
|
|
cpu->mts_shutdown = MTS_PROTO(shutdown); |
660 |
|
|
|
661 |
dpavlin |
7 |
/* Rebuild MTS data structures */ |
662 |
|
|
cpu->gen->mts_rebuild = MTS_PROTO(api_rebuild); |
663 |
|
|
|
664 |
dpavlin |
4 |
/* Show statistics */ |
665 |
dpavlin |
7 |
cpu->gen->mts_show_stats = MTS_PROTO(show_stats); |
666 |
dpavlin |
4 |
|
667 |
|
|
/* Load Operations */ |
668 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LB] = MTS_PROTO(lb); |
669 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LBU] = MTS_PROTO(lbu); |
670 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LH] = MTS_PROTO(lh); |
671 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LHU] = MTS_PROTO(lhu); |
672 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LW] = MTS_PROTO(lw); |
673 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LWU] = MTS_PROTO(lwu); |
674 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LD] = MTS_PROTO(ld); |
675 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LDL] = MTS_PROTO(ldl); |
676 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LDR] = MTS_PROTO(ldr); |
677 |
|
|
|
678 |
|
|
/* Store Operations */ |
679 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SB] = MTS_PROTO(sb); |
680 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SH] = MTS_PROTO(sh); |
681 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SW] = MTS_PROTO(sw); |
682 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SD] = MTS_PROTO(sd); |
683 |
|
|
|
684 |
|
|
/* Load Left/Right operations */ |
685 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LWL] = MTS_PROTO(lwl); |
686 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LWR] = MTS_PROTO(lwr); |
687 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LDL] = MTS_PROTO(ldl); |
688 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LDR] = MTS_PROTO(ldr); |
689 |
|
|
|
690 |
|
|
/* Store Left/Right operations */ |
691 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SWL] = MTS_PROTO(swl); |
692 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SWR] = MTS_PROTO(swr); |
693 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SDL] = MTS_PROTO(sdl); |
694 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SDR] = MTS_PROTO(sdr); |
695 |
|
|
|
696 |
|
|
/* LL/SC - Load Linked / Store Conditional */ |
697 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LL] = MTS_PROTO(ll); |
698 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SC] = MTS_PROTO(sc); |
699 |
|
|
|
700 |
|
|
/* Coprocessor 1 memory access functions */ |
701 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_LDC1] = MTS_PROTO(ldc1); |
702 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_SDC1] = MTS_PROTO(sdc1); |
703 |
|
|
|
704 |
|
|
/* Cache Operation */ |
705 |
|
|
cpu->mem_op_fn[MIPS_MEMOP_CACHE] = MTS_PROTO(cache); |
706 |
|
|
} |
707 |
|
|
|
708 |
|
|
#undef MTS_ADDR_SIZE |
709 |
dpavlin |
7 |
#undef MTS_NAME |
710 |
|
|
#undef MTS_NAME_UP |
711 |
dpavlin |
4 |
#undef MTS_PROTO |
712 |
|
|
#undef MTS_PROTO_UP |
713 |
|
|
#undef MTS_ENTRY |
714 |
|
|
#undef MTS_CHUNK |