29 |
/* Device ID mask and shift, device offset mask */ |
/* Device ID mask and shift, device offset mask */ |
30 |
#define MTS_DEVID_MASK 0xfc000000 |
#define MTS_DEVID_MASK 0xfc000000 |
31 |
#define MTS_DEVID_SHIFT 26 |
#define MTS_DEVID_SHIFT 26 |
32 |
#define MTS_DEVOFF_MASK 0x03fffff0 |
#define MTS_DEVOFF_MASK 0x03ffffff |
33 |
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|
34 |
/* Memory access flags */ |
/* Memory access flags */ |
|
#define MTS_ACC_OK 0x00000000 /* Access OK */ |
|
35 |
#define MTS_ACC_AE 0x00000002 /* Address Error */ |
#define MTS_ACC_AE 0x00000002 /* Address Error */ |
36 |
#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
37 |
#define MTS_ACC_U 0x00000006 /* Unexistent */ |
#define MTS_ACC_U 0x00000006 /* Unexistent */ |