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/* |
/* |
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* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
* |
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* Generic Cisco 7200 routines and definitions (EEPROM,...). |
* Generic Cisco 7200 routines and definitions (EEPROM,...). |
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#include "net.h" |
#include "net.h" |
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#include "device.h" |
#include "device.h" |
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#include "pci_dev.h" |
#include "pci_dev.h" |
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#include "nmc93c46.h" |
#include "nmc93cX6.h" |
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#include "dev_mv64460.h" |
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#include "net_io.h" |
#include "net_io.h" |
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#include "vm.h" |
#include "vm.h" |
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/* 6 slots + 1 I/O card */ |
/* 6 slots + 1 I/O card */ |
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#define C7200_MAX_PA_BAYS 7 |
#define C7200_MAX_PA_BAYS 7 |
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/* C7200 Timer IRQ (virtual) */ |
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#define C7200_VTIMER_IRQ 0 |
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/* C7200 DUART Interrupt */ |
/* C7200 DUART Interrupt */ |
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#define C7200_DUART_IRQ 5 |
#define C7200_DUART_IRQ 5 |
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/* C7200 Error/OIR Interrupt */ |
/* C7200 Error/OIR Interrupt */ |
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#define C7200_OIR_IRQ 6 |
#define C7200_OIR_IRQ 6 |
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/* Network IRQ */ |
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#define C7200_NETIO_IRQ_BASE 32 |
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#define C7200_NETIO_IRQ_PORT_BITS 3 |
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#define C7200_NETIO_IRQ_PORT_MASK ((1 << C7200_NETIO_IRQ_PORT_BITS) - 1) |
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#define C7200_NETIO_IRQ_PER_SLOT (1 << C7200_NETIO_IRQ_PORT_BITS) |
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#define C7200_NETIO_IRQ_END \ |
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(C7200_NETIO_IRQ_BASE + (C7200_MAX_PA_BAYS * C7200_NETIO_IRQ_PER_SLOT) - 1) |
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/* C7200 base ram limit (256 Mb) */ |
/* C7200 base ram limit (256 Mb) */ |
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#define C7200_BASE_RAM_LIMIT 256 |
#define C7200_BASE_RAM_LIMIT 256 |
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/* C7200 common device addresses */ |
/* C7200 common device addresses */ |
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#define C7200_GT64K_ADDR 0x14000000ULL |
#define C7200_GT64K_ADDR 0x14000000ULL |
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#define C7200_GT64K_SEC_ADDR 0x15000000ULL |
#define C7200_GT64K_SEC_ADDR 0x15000000ULL |
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#define C7200_BOOTFLASH_ADDR 0x1a000000ULL |
#define C7200_BOOTFLASH_ADDR 0x1a000000ULL |
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#define C7200_NVRAM_ADDR 0x1e000000ULL |
#define C7200_NVRAM_ADDR 0x1e000000ULL |
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#define C7200_NPEG1_NVRAM_ADDR 0x1e400000ULL |
#define C7200_MPFPGA_ADDR 0x1e800000ULL |
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#define C7200_MPFPGA_ADDR 0x1e800000ULL |
#define C7200_IOFPGA_ADDR 0x1e840000ULL |
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#define C7200_IOFPGA_ADDR 0x1e840000ULL |
#define C7200_BITBUCKET_ADDR 0x1f000000ULL |
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#define C7200_BITBUCKET_ADDR 0x1f000000ULL |
#define C7200_ROM_ADDR 0x1fc00000ULL |
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#define C7200_ROM_ADDR 0x1fc00000ULL |
#define C7200_IOMEM_ADDR 0x20000000ULL |
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#define C7200_IOMEM_ADDR 0x20000000ULL |
#define C7200_SRAM_ADDR 0x4b000000ULL |
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#define C7200_SRAM_ADDR 0x4b000000ULL |
#define C7200_BSWAP_ADDR 0xc0000000ULL |
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#define C7200_PCI_IO_ADDR 0x100000000ULL |
#define C7200_PCI_IO_ADDR 0x100000000ULL |
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/* NPE-G1 specific info */ |
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#define C7200_G1_NVRAM_ADDR 0x1e400000ULL |
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/* NPE-G2 specific info */ |
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#define C7200_G2_BSWAP_ADDR 0xc0000000ULL |
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#define C7200_G2_BOOTFLASH_ADDR 0xe8000000ULL |
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#define C7200_G2_PCI_IO_ADDR 0xf0000000ULL |
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#define C7200_G2_MV64460_ADDR 0xf1000000ULL |
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#define C7200_G2_MPFPGA_ADDR 0xfe000000ULL |
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#define C7200_G2_IOFPGA_ADDR 0xfe040000ULL |
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#define C7200_G2_NVRAM_ADDR 0xff000000ULL |
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#define C7200_G2_ROM_ADDR 0xfff00000ULL |
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/* NVRAM size for NPE-G2: 2 Mb */ |
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#define C7200_G2_NVRAM_SIZE (2 * 1048576) |
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/* Reserved space for ROM in NVRAM */ |
/* Reserved space for ROM in NVRAM */ |
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#define C7200_NVRAM_ROM_RES_SIZE 2048 |
#define C7200_NVRAM_ROM_RES_SIZE 2048 |
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/* C7200 ELF Platform ID */ |
/* C7200 ELF Platform ID */ |
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#define C7200_ELF_MACHINE_ID 0x19 |
#define C7200_ELF_MACHINE_ID 0x19 |
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/* NPE families */ |
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enum { |
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C7200_NPE_FAMILY_MIPS = 0, |
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C7200_NPE_FAMILY_PPC, |
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}; |
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/* C7200 router */ |
/* C7200 router */ |
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typedef struct c7200_router c7200_t; |
typedef struct c7200_router c7200_t; |
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/* C7200 EEPROM */ |
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struct c7200_eeprom { |
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char *name; |
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m_uint16_t *data; |
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u_int len; |
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}; |
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/* Prototype of NPE driver initialization function */ |
/* Prototype of NPE driver initialization function */ |
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typedef int (*c7200_npe_init_fn)(c7200_t *router); |
typedef int (*c7200_npe_init_fn)(c7200_t *router); |
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typedef int (*c7200_pa_unset_nio_fn)(c7200_t *router,u_int pa_bay, |
typedef int (*c7200_pa_unset_nio_fn)(c7200_t *router,u_int pa_bay, |
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u_int port_id); |
u_int port_id); |
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/* Prototype of NM NIO show info function */ |
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typedef int (*c7200_pa_show_info_fn)(c7200_t *router,u_int pa_bay); |
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/* C7200 Port Adapter Driver */ |
/* C7200 Port Adapter Driver */ |
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struct c7200_pa_driver { |
struct c7200_pa_driver { |
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char *dev_type; |
char *dev_type; |
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c7200_pa_shutdown_fn pa_shutdown; |
c7200_pa_shutdown_fn pa_shutdown; |
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c7200_pa_set_nio_fn pa_set_nio; |
c7200_pa_set_nio_fn pa_set_nio; |
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c7200_pa_unset_nio_fn pa_unset_nio; |
c7200_pa_unset_nio_fn pa_unset_nio; |
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c7200_pa_show_info_fn pa_show_info; |
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}; |
}; |
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/* C7200 NIO binding to a slot/port */ |
/* C7200 NIO binding to a slot/port */ |
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struct c7200_pa_bay { |
struct c7200_pa_bay { |
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char *dev_name; /* Device Name */ |
char *dev_name; /* Device Name */ |
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char *dev_type; /* Device Type */ |
char *dev_type; /* Device Type */ |
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struct cisco_eeprom eeprom; /* PA EEPROM */ |
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struct pci_bus *pci_map; /* PCI bus */ |
struct pci_bus *pci_map; /* PCI bus */ |
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struct nmc93c46_eeprom_def eeprom; /* PA EEPROM */ |
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struct c7200_pa_driver *pa_driver; /* PA driver */ |
struct c7200_pa_driver *pa_driver; /* PA driver */ |
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void *drv_info; /* Private driver info */ |
void *drv_info; /* Private driver info */ |
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struct c7200_nio_binding *nio_list; /* NIO bindings to ports */ |
struct c7200_nio_binding *nio_list; /* NIO bindings to ports */ |
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/* C7200 NPE Driver */ |
/* C7200 NPE Driver */ |
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struct c7200_npe_driver { |
struct c7200_npe_driver { |
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char *npe_type; |
char *npe_type; |
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int npe_family; |
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c7200_npe_init_fn npe_init; |
c7200_npe_init_fn npe_init; |
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int max_ram_size; |
int max_ram_size; |
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int supported; |
int supported; |
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m_uint64_t nvram_addr; |
m_uint64_t nvram_addr; |
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int iocard_required; |
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int clpd6729_pci_bus; |
int clpd6729_pci_bus; |
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int clpd6729_pci_dev; |
int clpd6729_pci_dev; |
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int dec21140_pci_bus; |
int dec21140_pci_bus; |
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/* Associated VM instance */ |
/* Associated VM instance */ |
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vm_instance_t *vm; |
vm_instance_t *vm; |
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/* MV64460 device for NPE-G2 */ |
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struct mv64460_data *mv64460_sysctr; |
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/* Midplane FPGA */ |
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struct c7200_mpfpga_data *mpfpga_data; |
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/* NPE and PA information */ |
/* NPE and PA information */ |
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struct c7200_npe_driver *npe_driver; |
struct c7200_npe_driver *npe_driver; |
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struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS]; |
struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS]; |
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struct pci_bus *pcmcia_bus; |
struct pci_bus *pcmcia_bus; |
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/* Midplane EEPROM can be modified to change the chassis MAC address... */ |
/* Midplane EEPROM can be modified to change the chassis MAC address... */ |
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m_uint16_t mp_eeprom_data[64]; |
struct cisco_eeprom cpu_eeprom,mp_eeprom,pem_eeprom; |
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struct nmc93c46_eeprom_def cpu_eeprom; /* CPU EEPROM */ |
struct nmc93cX6_group sys_eeprom_g1; /* EEPROMs for CPU and Midplane */ |
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struct nmc93c46_eeprom_def mp_eeprom; /* Midplane EEPROM */ |
struct nmc93cX6_group sys_eeprom_g2; /* EEPROM for PEM */ |
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struct nmc93c46_eeprom_def pem_eeprom; /* Power Entry Module EEPROM */ |
struct nmc93cX6_group pa_eeprom_g1; /* EEPROMs for bays 0, 1, 3, 4 */ |
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struct nmc93cX6_group pa_eeprom_g2; /* EEPROMs for bays 2, 5, 6 */ |
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struct nmc93c46_group sys_eeprom_g1; /* EEPROMs for CPU and Midplane */ |
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struct nmc93c46_group sys_eeprom_g2; /* EEPROM for PEM */ |
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struct nmc93c46_group pa_eeprom_g1; /* EEPROMs for bays 0, 1, 3, 4 */ |
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struct nmc93c46_group pa_eeprom_g2; /* EEPROMs for bays 2, 5, 6 */ |
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}; |
}; |
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/* Initialize EEPROM groups */ |
/* Initialize EEPROM groups */ |
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void c7200_init_eeprom_groups(c7200_t *router); |
void c7200_init_eeprom_groups(c7200_t *router); |
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/* Find an EEPROM in the specified array */ |
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struct c7200_eeprom *c7200_get_eeprom(struct c7200_eeprom *eeproms,char *name); |
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/* Get an EEPROM for a given NPE model */ |
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struct c7200_eeprom *c7200_get_cpu_eeprom(char *npe_name); |
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/* Get an EEPROM for a given midplane model */ |
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struct c7200_eeprom *c7200_get_midplane_eeprom(char *midplane_name); |
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/* Get a PEM EEPROM for a given NPE model */ |
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struct c7200_eeprom *c7200_get_pem_eeprom(char *npe_name); |
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/* Create a new router instance */ |
/* Create a new router instance */ |
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c7200_t *c7200_create_instance(char *name,int instance_id); |
c7200_t *c7200_create_instance(char *name,int instance_id); |
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/* Save configurations of all C7200 instances */ |
/* Save configurations of all C7200 instances */ |
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void c7200_save_config_all(FILE *fd); |
void c7200_save_config_all(FILE *fd); |
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/* Get network IRQ for specified slot/port */ |
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u_int c7200_net_irq_for_slot_port(u_int slot,u_int port); |
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/* Set PA EEPROM definition */ |
/* Set PA EEPROM definition */ |
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int c7200_pa_set_eeprom(c7200_t *router,u_int pa_bay, |
int c7200_pa_set_eeprom(c7200_t *router,u_int pa_bay, |
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const struct c7200_eeprom *eeprom); |
const struct cisco_eeprom *eeprom); |
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/* Unset PA EEPROM definition (empty bay) */ |
/* Unset PA EEPROM definition (empty bay) */ |
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int c7200_pa_unset_eeprom(c7200_t *router,u_int pa_bay); |
int c7200_pa_unset_eeprom(c7200_t *router,u_int pa_bay); |
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/* Shutdown all PA of a router */ |
/* Shutdown all PA of a router */ |
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int c7200_pa_shutdown_all(c7200_t *router); |
int c7200_pa_shutdown_all(c7200_t *router); |
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/* Show info about all NMs */ |
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int c7200_pa_show_all_info(c7200_t *router); |
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/* Create a Port Adapter (command line) */ |
/* Create a Port Adapter (command line) */ |
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int c7200_cmd_pa_create(c7200_t *router,char *str); |
int c7200_cmd_pa_create(c7200_t *router,char *str); |
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/* Initialize default parameters for a C7200 */ |
/* Initialize default parameters for a C7200 */ |
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void c7200_init_defaults(c7200_t *router); |
void c7200_init_defaults(c7200_t *router); |
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/* Initialize the C7200 Platform */ |
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int c7200_init_platform(c7200_t *router); |
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/* Boot the IOS image */ |
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int c7200_boot_ios(c7200_t *router); |
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/* Initialize a Cisco 7200 instance */ |
/* Initialize a Cisco 7200 instance */ |
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int c7200_init_instance(c7200_t *router); |
int c7200_init_instance(c7200_t *router); |
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/* dev_c7200_iofpga_init() */ |
/* dev_c7200_iofpga_init() */ |
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int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len); |
int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len); |
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/* dev_mpfpga_init() */ |
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int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len); |
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/* PA drivers */ |
/* PA drivers */ |
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extern struct c7200_pa_driver dev_c7200_io_fe_driver; |
extern struct c7200_pa_driver dev_c7200_iocard_fe_driver; |
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extern struct c7200_pa_driver dev_c7200_iocard_2fe_driver; |
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extern struct c7200_pa_driver dev_c7200_iocard_ge_e_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_fe_tx_driver; |
extern struct c7200_pa_driver dev_c7200_pa_fe_tx_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_2fe_tx_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_ge_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_4e_driver; |
extern struct c7200_pa_driver dev_c7200_pa_4e_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_8e_driver; |
extern struct c7200_pa_driver dev_c7200_pa_8e_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_4t_driver; |
extern struct c7200_pa_driver dev_c7200_pa_4t_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_a1_driver; |
extern struct c7200_pa_driver dev_c7200_pa_a1_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_pos_oc3_driver; |
extern struct c7200_pa_driver dev_c7200_pa_pos_oc3_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_4b_driver; |
extern struct c7200_pa_driver dev_c7200_pa_4b_driver; |
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extern struct c7200_pa_driver dev_c7200_pa_mc8te1_driver; |
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#endif |
#endif |