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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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|
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#ifndef __PPC32_X86_TRANS_H__ |
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#define __PPC32_X86_TRANS_H__ |
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|
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#include "utils.h" |
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#include "x86-codegen.h" |
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#include "cpu.h" |
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#include "ppc32_exec.h" |
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#include "dynamips.h" |
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|
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#define JIT_SUPPORT 1 |
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|
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/* Manipulate bitmasks atomically */ |
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static forced_inline void atomic_or(m_uint32_t *v,m_uint32_t m) |
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{ |
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__asm__ __volatile__("lock; orl %1,%0":"=m"(*v):"ir"(m),"m"(*v)); |
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} |
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|
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static forced_inline void atomic_and(m_uint32_t *v,m_uint32_t m) |
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{ |
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__asm__ __volatile__("lock; andl %1,%0":"=m"(*v):"ir"(m),"m"(*v)); |
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} |
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|
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/* Wrappers to x86-codegen functions */ |
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#define ppc32_jit_tcb_set_patch x86_patch |
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#define ppc32_jit_tcb_set_jump x86_jump_code |
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|
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/* PPC instruction array */ |
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extern struct ppc32_insn_tag ppc32_insn_tags[]; |
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|
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/* Push epilog for an x86 instruction block */ |
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static forced_inline void ppc32_jit_tcb_push_epilog(ppc32_jit_tcb_t *block) |
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{ |
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x86_ret(block->jit_ptr); |
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} |
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|
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/* Execute JIT code */ |
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static forced_inline |
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void ppc32_jit_tcb_exec(cpu_ppc_t *cpu,ppc32_jit_tcb_t *block) |
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{ |
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insn_tblock_fptr jit_code; |
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m_uint32_t offset; |
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|
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offset = (cpu->ia & PPC32_MIN_PAGE_IMASK) >> 2; |
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jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset]; |
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|
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#if 0 |
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if (unlikely(!jit_code)) { |
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ppc32_exec_single_step(cpu,vmtoh32(block->ppc_code[offset])); |
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return; |
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} |
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#endif |
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|
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asm volatile ("movl %0,%%edi"::"r"(cpu): |
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"esi","edi","eax","ebx","ecx","edx"); |
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jit_code(); |
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} |
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|
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/* Set the Instruction Address (IA) register */ |
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void ppc32_set_ia(ppc32_jit_tcb_t *b,m_uint32_t new_ia); |
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|
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/* Set the Link Register (LR) */ |
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void ppc32_set_lr(ppc32_jit_tcb_t *b,m_uint32_t new_lr); |
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|
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/* Increment the number of executed instructions (performance debugging) */ |
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void ppc32_inc_perf_counter(ppc32_jit_tcb_t *b); |
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|
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#endif |