/[dynamips]/upstream/dynamips-0.2.7-RC3/ppc32_amd64_trans.h
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Diff of /upstream/dynamips-0.2.7-RC3/ppc32_amd64_trans.h

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upstream/dynamips-0.2.7-RC2/ppc32_amd64_trans.h revision 8 by dpavlin, Sat Oct 6 16:24:54 2007 UTC upstream/dynamips-0.2.7-RC3/ppc32_amd64_trans.h revision 9 by dpavlin, Sat Oct 6 16:26:06 2007 UTC
# Line 33  static forced_inline void atomic_and(m_u Line 33  static forced_inline void atomic_and(m_u
33  extern struct ppc32_insn_tag ppc32_insn_tags[];  extern struct ppc32_insn_tag ppc32_insn_tags[];
34    
35  /* Push epilog for an x86 instruction block */  /* Push epilog for an x86 instruction block */
36  static forced_inline void ppc32_jit_tcb_push_epilog(ppc32_jit_tcb_t *block)  static forced_inline void ppc32_jit_tcb_push_epilog(u_char **ptr)
37  {  {
38     amd64_ret(block->jit_ptr);     amd64_ret(*ptr);
39  }  }
40    
41  /* Execute JIT code */  /* Execute JIT code */
# Line 48  void ppc32_jit_tcb_exec(cpu_ppc_t *cpu,p Line 48  void ppc32_jit_tcb_exec(cpu_ppc_t *cpu,p
48     offset = (cpu->ia & PPC32_MIN_PAGE_IMASK) >> 2;     offset = (cpu->ia & PPC32_MIN_PAGE_IMASK) >> 2;
49     jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset];     jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset];
50    
 #if 0  
51     if (unlikely(!jit_code)) {     if (unlikely(!jit_code)) {
52        ppc32_exec_single_step(cpu,vmtoh32(block->ppc_code[offset]));        ppc32_jit_tcb_set_target_bit(block,cpu->ia);
53        return;  
54          if (++block->target_undef_cnt == 16) {
55             ppc32_jit_tcb_recompile(cpu,block);
56             jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset];
57          } else {
58             ppc32_exec_page(cpu);
59             return;
60          }
61     }     }
 #endif  
62    
63     asm volatile ("movq %0,%%r15"::"r"(cpu):     asm volatile ("movq %0,%%r15"::"r"(cpu):
64                   "r14","r15","rax","rbx","rcx","rdx","rdi","rsi");                   "r13","r14","r15","rax","rbx","rcx","rdx","rdi","rsi");
65     jit_code();     jit_code();
66  }  }
67    
# Line 82  static inline void amd64_patch(u_char *c Line 87  static inline void amd64_patch(u_char *c
87        x86_patch(code,target);        x86_patch(code,target);
88  }  }
89    
 /* Set the Instruction Address (IA) register */  
 void ppc32_set_ia(ppc32_jit_tcb_t *b,m_uint32_t new_ia);  
   
 /* Set the Link Register (LR) */  
 void ppc32_set_lr(ppc32_jit_tcb_t *b,m_uint32_t new_lr);  
   
 /* Increment the number of executed instructions (performance debugging) */  
 void ppc32_inc_perf_counter(ppc32_jit_tcb_t *b);  
   
90  #endif  #endif

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