/[dynamips]/upstream/dynamips-0.2.7-RC2/ppc32.h
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Annotation of /upstream/dynamips-0.2.7-RC2/ppc32.h

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Revision 8 - (hide annotations)
Sat Oct 6 16:24:54 2007 UTC (13 years, 1 month ago) by dpavlin
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dynamips-0.2.7-RC2

1 dpavlin 7 /*
2     * Cisco router simulation platform.
3     * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4     */
5    
6     #ifndef __PPC_32_H__
7     #define __PPC_32_H__
8    
9     #include <pthread.h>
10    
11     #include "utils.h"
12     #include "rbtree.h"
13    
14     /* CPU identifiers */
15     #define PPC32_PVR_405 0x40110000
16    
17     /* Number of GPR (general purpose registers) */
18     #define PPC32_GPR_NR 32
19    
20     /* Number of registers in FPU */
21     #define PPC32_FPU_REG_NR 32
22    
23     /* Minimum page size: 4 Kb */
24     #define PPC32_MIN_PAGE_SHIFT 12
25     #define PPC32_MIN_PAGE_SIZE (1 << PPC32_MIN_PAGE_SHIFT)
26     #define PPC32_MIN_PAGE_IMASK (PPC32_MIN_PAGE_SIZE - 1)
27     #define PPC32_MIN_PAGE_MASK 0xFFFFF000
28    
29     /* Starting point for ROM */
30     #define PPC32_ROM_START 0xfff00100
31     #define PPC32_ROM_SP 0x00006000
32    
33     /* Special Purpose Registers (SPR) */
34     #define PPC32_SPR_XER 1
35     #define PPC32_SPR_LR 8 /* Link Register */
36     #define PPC32_SPR_CTR 9 /* Count Register */
37     #define PPC32_SPR_DSISR 18
38     #define PPC32_SPR_DAR 19
39     #define PPC32_SPR_DEC 22 /* Decrementer */
40     #define PPC32_SPR_SDR1 25 /* Page Table Address */
41     #define PPC32_SPR_SRR0 26
42     #define PPC32_SPR_SRR1 27
43     #define PPC32_SPR_TBL_READ 268 /* Time Base Low (read) */
44     #define PPC32_SPR_TBU_READ 269 /* Time Base Up (read) */
45     #define PPC32_SPR_SPRG0 272
46     #define PPC32_SPR_SPRG1 273
47     #define PPC32_SPR_SPRG2 274
48     #define PPC32_SPR_SPRG3 275
49     #define PPC32_SPR_TBL_WRITE 284 /* Time Base Low (write) */
50     #define PPC32_SPR_TBU_WRITE 285 /* Time Base Up (write) */
51     #define PPC32_SPR_PVR 287 /* Processor Version Register */
52     #define PPC32_SPR_HID0 1008
53     #define PPC32_SPR_HID1 1009
54    
55     #define PPC405_SPR_PID 945 /* Process Identifier */
56    
57     /* Exception vectors */
58     #define PPC32_EXC_SYS_RST 0x00000100 /* System Reset */
59     #define PPC32_EXC_MC_CHK 0x00000200 /* Machine Check */
60     #define PPC32_EXC_DSI 0x00000300 /* Data memory access failure */
61     #define PPC32_EXC_ISI 0x00000400 /* Instruction fetch failure */
62     #define PPC32_EXC_EXT 0x00000500 /* External Interrupt */
63     #define PPC32_EXC_ALIGN 0x00000600 /* Alignment */
64     #define PPC32_EXC_PROG 0x00000700 /* FPU, Illegal instruction, ... */
65     #define PPC32_EXC_NO_FPU 0x00000800 /* FPU unavailable */
66     #define PPC32_EXC_DEC 0x00000900 /* Decrementer */
67     #define PPC32_EXC_SYSCALL 0x00000C00 /* System Call */
68     #define PPC32_EXC_TRACE 0x00000D00 /* Trace */
69     #define PPC32_EXC_FPU_HLP 0x00000E00 /* Floating-Point Assist */
70    
71 dpavlin 8 /* Condition Register (CR) is accessed through 8 fields of 4 bits */
72     #define ppc32_get_cr_field(n) ((n) >> 2)
73     #define ppc32_get_cr_bit(n) (~(n) & 0x03)
74    
75     /* Positions of LT, GT, EQ and SO bits in CR fields */
76     #define PPC32_CR_LT_BIT 3
77     #define PPC32_CR_GT_BIT 2
78     #define PPC32_CR_EQ_BIT 1
79     #define PPC32_CR_SO_BIT 0
80    
81 dpavlin 7 /* CR0 (Condition Register Field 0) bits */
82     #define PPC32_CR0_LT_BIT 31
83     #define PPC32_CR0_LT (1 << PPC32_CR0_LT_BIT) /* Negative */
84     #define PPC32_CR0_GT_BIT 30
85     #define PPC32_CR0_GT (1 << PPC32_CR0_GT_BIT) /* Positive */
86     #define PPC32_CR0_EQ_BIT 29
87     #define PPC32_CR0_EQ (1 << PPC32_CR0_EQ_BIT) /* Zero */
88     #define PPC32_CR0_SO_BIT 28
89     #define PPC32_CR0_SO (1 << PPC32_CR0_SO_BIT) /* Summary overflow */
90    
91     /* XER register */
92     #define PPC32_XER_SO_BIT 31
93     #define PPC32_XER_SO (1 << PPC32_XER_SO_BIT) /* Summary Overflow */
94     #define PPC32_XER_OV 0x40000000 /* Overflow */
95     #define PPC32_XER_CA_BIT 29
96     #define PPC32_XER_CA (1 << PPC32_XER_CA_BIT) /* Carry */
97     #define PPC32_XER_BC_MASK 0x0000007F /* Byte cnt (lswx/stswx) */
98    
99     /* MSR (Machine State Register) */
100     #define PPC32_MSR_POW_MASK 0x00060000 /* Power Management */
101     #define PPC32_MSR_ILE 0x00010000 /* Exception Little-Endian Mode */
102     #define PPC32_MSR_EE 0x00008000 /* External Interrupt Enable */
103     #define PPC32_MSR_PR 0x00004000 /* Privilege Level (0=supervisor) */
104     #define PPC32_MSR_PR_SHIFT 14
105     #define PPC32_MSR_FP 0x00002000 /* Floating-Point Available */
106     #define PPC32_MSR_ME 0x00001000 /* Machine Check Enable */
107     #define PPC32_MSR_FE0 0x00000800 /* Floating-Point Exception Mode 0 */
108     #define PPC32_MSR_SE 0x00000400 /* Single-step trace enable */
109     #define PPC32_MSR_BE 0x00000200 /* Branch Trace Enable */
110     #define PPC32_MSR_FE1 0x00000100 /* Floating-Point Exception Mode 1 */
111     #define PPC32_MSR_IP 0x00000040 /* Exception Prefix */
112     #define PPC32_MSR_IR 0x00000020 /* Instruction address translation */
113     #define PPC32_MSR_DR 0x00000010 /* Data address translation */
114     #define PPC32_MSR_RI 0x00000002 /* Recoverable Exception */
115     #define PPC32_MSR_LE 0x00000001 /* Little-Endian mode enable */
116    
117     #define PPC32_RFI_MSR_MASK 0x87c0ff73
118     #define PPC32_EXC_SRR1_MASK 0x0000ff73
119     #define PPC32_EXC_MSR_MASK 0x0006ef32
120    
121     /* Number of BAT registers (8 for PowerPC 7448) */
122     #define PPC32_BAT_NR 8
123    
124     /* Number of segment registers */
125     #define PPC32_SR_NR 16
126    
127     /* Upper BAT register */
128     #define PPC32_UBAT_BEPI_MASK 0xFFFE0000 /* Block Effective Page Index */
129     #define PPC32_UBAT_BEPI_SHIFT 17
130     #define PPC32_UBAT_BL_MASK 0x00001FFC /* Block Length */
131     #define PPC32_UBAT_BL_SHIFT 2
132     #define PPC32_UBAT_XBL_MASK 0x0001FFFC /* Block Length */
133     #define PPC32_UBAT_XBL_SHIFT 2
134     #define PPC32_UBAT_VS 0x00000002 /* Supervisor mode valid bit */
135     #define PPC32_UBAT_VP 0x00000001 /* User mode valid bit */
136     #define PPC32_UBAT_PROT_MASK (PPC32_UBAT_VS|PPC32_UBAT_VP)
137    
138     /* Lower BAT register */
139     #define PPC32_LBAT_BRPN_MASK 0xFFFE0000 /* Physical address */
140     #define PPC32_LBAT_BRPN_SHIFT 17
141     #define PPC32_LBAT_WIMG_MASK 0x00000078 /* Memory/cache access mode bits */
142     #define PPC32_LBAT_PP_MASK 0x00000003 /* Protection bits */
143    
144     #define PPC32_BAT_ADDR_SHIFT 17
145    
146     /* Segment Descriptor */
147     #define PPC32_SD_T 0x80000000
148     #define PPC32_SD_KS 0x40000000 /* Supervisor-state protection key */
149     #define PPC32_SD_KP 0x20000000 /* User-state protection key */
150     #define PPC32_SD_N 0x10000000 /* No-execute protection bit */
151     #define PPC32_SD_VSID_MASK 0x00FFFFFF /* Virtual Segment ID */
152    
153     /* SDR1 Register */
154     #define PPC32_SDR1_HTABORG_MASK 0xFFFF0000 /* Physical base address */
155     #define PPC32_SDR1_HTABEXT_MASK 0x0000E000 /* Extended base address */
156     #define PPC32_SDR1_HTABMASK 0x000001FF /* Mask for page table address */
157     #define PPC32_SDR1_HTMEXT_MASK 0x00001FFF /* Extended mask */
158    
159     /* Page Table Entry (PTE) size: 64-bits */
160     #define PPC32_PTE_SIZE 8
161    
162     /* PTE entry (Up and Lo) */
163     #define PPC32_PTEU_V 0x80000000 /* Valid entry */
164     #define PPC32_PTEU_VSID_MASK 0x7FFFFF80 /* Virtual Segment ID */
165     #define PPC32_PTEU_VSID_SHIFT 7
166     #define PPC32_PTEU_H 0x00000040 /* Hash function */
167     #define PPC32_PTEU_API_MASK 0x0000003F /* Abbreviated Page index */
168     #define PPC32_PTEL_RPN_MASK 0xFFFFF000 /* Physical Page Number */
169     #define PPC32_PTEL_XPN_MASK 0x00000C00 /* Extended Page Number (0-2) */
170     #define PPC32_PTEL_XPN_SHIFT 9
171     #define PPC32_PTEL_R 0x00000100 /* Referenced bit */
172     #define PPC32_PTEL_C 0x00000080 /* Changed bit */
173     #define PPC32_PTEL_WIMG_MASK 0x00000078 /* Mem/cache access mode bits */
174     #define PPC32_PTEL_WIMG_SHIFT 3
175     #define PPC32_PTEL_X_MASK 0x00000004 /* Extended Page Number (3) */
176     #define PPC32_PTEL_X_SHIFT 2
177     #define PPC32_PTEL_PP_MASK 0x00000003 /* Page Protection bits */
178    
179     /* DSISR register */
180     #define PPC32_DSISR_NOTRANS 0x40000000 /* No valid translation */
181     #define PPC32_DSISR_STORE 0x02000000 /* Store operation */
182    
183     /* PowerPC 405 TLB definitions */
184     #define PPC405_TLBHI_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
185     #define PPC405_TLBHI_SIZE_MASK 0x00000380 /* Page Size */
186     #define PPC405_TLBHI_SIZE_SHIFT 7
187     #define PPC405_TLBHI_V 0x00000040 /* Valid TLB entry */
188     #define PPC405_TLBHI_E 0x00000020 /* Endianness */
189     #define PPC405_TLBHI_U0 0x00000010 /* User-Defined Attribute */
190    
191     #define PPC405_TLBLO_RPN_MASK 0xFFFFFC00 /* Real Page Number */
192     #define PPC405_TLBLO_EX 0x00000200 /* Execute Enable */
193     #define PPC405_TLBLO_WR 0x00000100 /* Write Enable */
194     #define PPC405_TLBLO_ZSEL_MASK 0x000000F0 /* Zone Select */
195     #define PPC405_TLBLO_ZSEL_SHIFT 4
196     #define PPC405_TLBLO_W 0x00000008 /* Write-Through */
197     #define PPC405_TLBLO_I 0x00000004 /* Caching Inhibited */
198     #define PPC405_TLBLO_M 0x00000002 /* Memory Coherent */
199     #define PPC405_TLBLO_G 0x00000001 /* Guarded */
200    
201     /* Number of TLB entries for PPC405 */
202     #define PPC405_TLB_ENTRIES 64
203    
204     struct ppc405_tlb_entry {
205     m_uint32_t tlb_hi,tlb_lo,tid;
206     };
207    
208     /* Memory operations */
209     enum {
210     PPC_MEMOP_LOOKUP = 0,
211    
212     /* Instruction fetch operation */
213     PPC_MEMOP_IFETCH,
214    
215     /* Load operations */
216     PPC_MEMOP_LBZ,
217     PPC_MEMOP_LHZ,
218     PPC_MEMOP_LWZ,
219    
220     /* Load operation with sign-extend */
221     PPC_MEMOP_LHA,
222    
223     /* Store operations */
224     PPC_MEMOP_STB,
225     PPC_MEMOP_STH,
226     PPC_MEMOP_STW,
227    
228     /* Byte-Reversed operations */
229     PPC_MEMOP_LWBR,
230     PPC_MEMOP_STWBR,
231    
232     /* String operations */
233     PPC_MEMOP_LSW,
234     PPC_MEMOP_STSW,
235    
236     /* FPU operations */
237     PPC_MEMOP_LFD,
238     PPC_MEMOP_STFD,
239    
240     /* ICBI - Instruction Cache Block Invalidate */
241     PPC_MEMOP_ICBI,
242    
243     PPC_MEMOP_MAX,
244     };
245    
246     /* PowerPC CPU type */
247     typedef struct cpu_ppc cpu_ppc_t;
248    
249     /* Memory operation function prototype */
250     typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
251     u_int reg);
252    
253     /* BAT type indexes */
254     enum {
255     PPC32_IBAT_IDX = 0,
256     PPC32_DBAT_IDX,
257     };
258    
259     /* BAT register */
260     struct ppc32_bat_reg {
261     m_uint32_t reg[2];
262     };
263    
264     /* BAT register programming */
265     struct ppc32_bat_prog {
266     int type,index;
267     m_uint32_t hi,lo;
268     };
269    
270     /* MTS Instruction Cache and Data Cache */
271     #define PPC32_MTS_ICACHE PPC32_IBAT_IDX
272     #define PPC32_MTS_DCACHE PPC32_DBAT_IDX
273    
274     /* FPU Coprocessor definition */
275     typedef struct {
276     m_uint64_t reg[PPC32_FPU_REG_NR];
277     }ppc_fpu_t;
278    
279     /* Maximum number of breakpoints */
280     #define PPC32_MAX_BREAKPOINTS 8
281    
282     /* PowerPC CPU definition */
283     struct cpu_ppc {
284     /* Instruction address */
285     m_uint32_t ia;
286    
287     /* General Purpose registers */
288     m_uint32_t gpr[PPC32_GPR_NR];
289    
290     /* Pending IRQ */
291     volatile m_uint32_t irq_pending,irq_check;
292    
293     /* XER, Condition Register, Link Register, Count Register */
294 dpavlin 8 m_uint32_t xer,lr,ctr,reserve;
295 dpavlin 7 m_uint32_t xer_ca;
296    
297 dpavlin 8 /* Condition Register (CR) fields */
298     u_int cr_fields[8];
299    
300 dpavlin 7 /* MTS caches (Instruction+Data) */
301     mts32_entry_t *mts_cache[2];
302    
303 dpavlin 8 /* Code page translation cache and physical page mapping */
304     ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map;
305 dpavlin 7
306     /* Virtual address to physical page translation */
307     fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
308     m_uint32_t *phys_page);
309    
310     /* Memory access functions */
311     ppc_memop_fn mem_op_fn[PPC_MEMOP_MAX];
312    
313     /* Memory lookup function (to load ELF image,...) */
314     void *(*mem_op_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid);
315    
316     /* MTS slow lookup function */
317     mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
318     u_int cid,u_int op_code,u_int op_size,
319     u_int op_type,m_uint64_t *data,
320     u_int *exc,mts32_entry_t *alt_entry);
321    
322     /* IRQ counters */
323     m_uint64_t irq_count,timer_irq_count,irq_fp_count;
324     pthread_mutex_t irq_lock;
325    
326     /* Current and free lists of translated code blocks */
327     ppc32_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list;
328    
329     /* Executable page area */
330     void *exec_page_area;
331     size_t exec_page_area_size;
332     size_t exec_page_count,exec_page_alloc;
333     insn_exec_page_t *exec_page_free_list;
334     insn_exec_page_t *exec_page_array;
335    
336     /* Idle PC value */
337     volatile m_uint32_t idle_pc;
338    
339     /* Timer IRQs */
340     volatile u_int timer_irq_pending,timer_irq_armed;
341     u_int timer_irq_freq;
342     u_int timer_irq_check_itv;
343     u_int timer_drift;
344    
345     /* IRQ disable flag */
346     volatile u_int irq_disable;
347    
348     /* IBAT (Instruction) and DBAT (Data) registers */
349     struct ppc32_bat_reg bat[2][PPC32_BAT_NR];
350    
351     /* Segment registers */
352     m_uint32_t sr[PPC32_SR_NR];
353    
354     /* Page Table Address */
355     m_uint32_t sdr1;
356     void *sdr1_hptr;
357    
358     /* MSR (Machine state register) */
359     m_uint32_t msr;
360    
361     /* Interrupt Registers (SRR0/SRR1) */
362     m_uint32_t srr0,srr1,dsisr,dar;
363    
364     /* SPRG registers */
365     m_uint32_t sprg[4];
366    
367     /* PVR (Processor Version Register) */
368     m_uint32_t pvr;
369    
370     /* Time-Base register */
371     m_uint64_t tb;
372    
373     /* Decrementer */
374     m_uint32_t dec;
375    
376     /* Hardware Implementation Dependent Registers */
377     m_uint32_t hid0,hid1;
378    
379     /* String instruction position (lswi/stswi) */
380     u_int sw_pos;
381    
382     /* PowerPC 405 TLB */
383     struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
384     m_uint32_t ppc405_pid;
385    
386     /* FPU */
387     ppc_fpu_t fpu;
388    
389     /* Generic CPU instance pointer */
390     cpu_gen_t *gen;
391    
392     /* VM instance */
393     vm_instance_t *vm;
394    
395     /* MTS cache statistics */
396     m_uint64_t mts_misses,mts_lookups;
397    
398     /* JIT flush method */
399     u_int jit_flush_method;
400    
401     /* Number of compiled pages */
402     u_int compiled_pages;
403    
404     /* Fast memory operations use */
405     u_int fast_memop;
406    
407 dpavlin 8 /* Direct block jump */
408     u_int exec_blk_direct_jump;
409 dpavlin 7
410     /* Current exec page (non-JIT) info */
411     m_uint64_t njm_exec_page;
412     mips_insn_t *njm_exec_ptr;
413    
414     /* Performance counter (non-JIT) */
415     m_uint64_t perf_counter;
416    
417     /* non-JIT mode instruction counter */
418     m_uint64_t insn_exec_count;
419    
420     /* Breakpoints */
421     m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
422     u_int breakpoints_enabled;
423     };
424    
425 dpavlin 8 #define PPC32_CR_FIELD_OFFSET(f) \
426     (OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int)))
427    
428     /* Get the full CR register */
429     static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu)
430     {
431     m_uint32_t cr = 0;
432     int i;
433    
434     for(i=0;i<8;i++)
435     cr |= cpu->cr_fields[i] << (28 - (i << 2));
436    
437     return(cr);
438     }
439    
440     /* Set the CR fields given a CR value */
441     static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr)
442     {
443     int i;
444    
445     for(i=0;i<8;i++)
446     cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F;
447     }
448    
449     /* Get a CR bit */
450     static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit)
451     {
452     m_uint32_t res;
453    
454     res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit);
455     return(res & 0x01);
456     }
457    
458     /* Set a CR bit */
459     static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit)
460     {
461     cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit);
462     }
463    
464     /* Clear a CR bit */
465     static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit)
466     {
467     cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit));
468     }
469    
470 dpavlin 7 /* Reset a PowerPC CPU */
471     int ppc32_reset(cpu_ppc_t *cpu);
472    
473     /* Initialize a PowerPC processor */
474     int ppc32_init(cpu_ppc_t *cpu);
475    
476     /* Delete a PowerPC processor */
477     void ppc32_delete(cpu_ppc_t *cpu);
478    
479     /* Set the processor version register (PVR) */
480     void ppc32_set_pvr(cpu_ppc_t *cpu,m_uint32_t pvr);
481    
482     /* Set idle PC value */
483     void ppc32_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr);
484    
485     /* Timer IRQ */
486     void *ppc32_timer_irq_run(cpu_ppc_t *cpu);
487    
488     /* Determine an "idling" PC */
489     int ppc32_get_idling_pc(cpu_gen_t *cpu);
490    
491     /* Generate an exception */
492     void ppc32_trigger_exception(cpu_ppc_t *cpu,u_int exc_vector);
493    
494     /* Trigger the decrementer exception */
495     void ppc32_trigger_timer_irq(cpu_ppc_t *cpu);
496    
497     /* Trigger IRQs */
498     fastcall void ppc32_trigger_irq(cpu_ppc_t *cpu);
499    
500     /* Virtual breakpoint */
501     fastcall void ppc32_run_breakpoint(cpu_ppc_t *cpu);
502    
503     /* Add a virtual breakpoint */
504     int ppc32_add_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);
505    
506     /* Remove a virtual breakpoint */
507     void ppc32_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);
508    
509     /* Set a register */
510     void ppc32_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val);
511    
512     /* Dump registers of a PowerPC processor */
513     void ppc32_dump_regs(cpu_gen_t *cpu);
514    
515     /* Dump MMU registers */
516     void ppc32_dump_mmu(cpu_gen_t *cpu);
517    
518     /* Load a raw image into the simulated memory */
519     int ppc32_load_raw_image(cpu_ppc_t *cpu,char *filename,m_uint32_t vaddr);
520    
521     /* Load an ELF image into the simulated memory */
522     int ppc32_load_elf_image(cpu_ppc_t *cpu,char *filename,int skip_load,
523     m_uint32_t *entry_point);
524    
525     /* Run PowerPC code in step-by-step mode */
526     void *ppc32_exec_run_cpu(cpu_gen_t *gen);
527    
528     #endif

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