/[dynamips]/upstream/dynamips-0.2.7-RC2/ppc32.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /upstream/dynamips-0.2.7-RC2/ppc32.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 7 - (show annotations)
Sat Oct 6 16:23:47 2007 UTC (13 years, 1 month ago) by dpavlin
Original Path: upstream/dynamips-0.2.7-RC1/ppc32.h
File MIME type: text/plain
File size: 15106 byte(s)
dynamips-0.2.7-RC1

1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4 */
5
6 #ifndef __PPC_32_H__
7 #define __PPC_32_H__
8
9 #include <pthread.h>
10
11 #include "utils.h"
12 #include "rbtree.h"
13
14 /* CPU identifiers */
15 #define PPC32_PVR_405 0x40110000
16
17 /* Number of GPR (general purpose registers) */
18 #define PPC32_GPR_NR 32
19
20 /* Number of registers in FPU */
21 #define PPC32_FPU_REG_NR 32
22
23 /* Minimum page size: 4 Kb */
24 #define PPC32_MIN_PAGE_SHIFT 12
25 #define PPC32_MIN_PAGE_SIZE (1 << PPC32_MIN_PAGE_SHIFT)
26 #define PPC32_MIN_PAGE_IMASK (PPC32_MIN_PAGE_SIZE - 1)
27 #define PPC32_MIN_PAGE_MASK 0xFFFFF000
28
29 /* Starting point for ROM */
30 #define PPC32_ROM_START 0xfff00100
31 #define PPC32_ROM_SP 0x00006000
32
33 /* Special Purpose Registers (SPR) */
34 #define PPC32_SPR_XER 1
35 #define PPC32_SPR_LR 8 /* Link Register */
36 #define PPC32_SPR_CTR 9 /* Count Register */
37 #define PPC32_SPR_DSISR 18
38 #define PPC32_SPR_DAR 19
39 #define PPC32_SPR_DEC 22 /* Decrementer */
40 #define PPC32_SPR_SDR1 25 /* Page Table Address */
41 #define PPC32_SPR_SRR0 26
42 #define PPC32_SPR_SRR1 27
43 #define PPC32_SPR_TBL_READ 268 /* Time Base Low (read) */
44 #define PPC32_SPR_TBU_READ 269 /* Time Base Up (read) */
45 #define PPC32_SPR_SPRG0 272
46 #define PPC32_SPR_SPRG1 273
47 #define PPC32_SPR_SPRG2 274
48 #define PPC32_SPR_SPRG3 275
49 #define PPC32_SPR_TBL_WRITE 284 /* Time Base Low (write) */
50 #define PPC32_SPR_TBU_WRITE 285 /* Time Base Up (write) */
51 #define PPC32_SPR_PVR 287 /* Processor Version Register */
52 #define PPC32_SPR_HID0 1008
53 #define PPC32_SPR_HID1 1009
54
55 #define PPC405_SPR_PID 945 /* Process Identifier */
56
57 /* Exception vectors */
58 #define PPC32_EXC_SYS_RST 0x00000100 /* System Reset */
59 #define PPC32_EXC_MC_CHK 0x00000200 /* Machine Check */
60 #define PPC32_EXC_DSI 0x00000300 /* Data memory access failure */
61 #define PPC32_EXC_ISI 0x00000400 /* Instruction fetch failure */
62 #define PPC32_EXC_EXT 0x00000500 /* External Interrupt */
63 #define PPC32_EXC_ALIGN 0x00000600 /* Alignment */
64 #define PPC32_EXC_PROG 0x00000700 /* FPU, Illegal instruction, ... */
65 #define PPC32_EXC_NO_FPU 0x00000800 /* FPU unavailable */
66 #define PPC32_EXC_DEC 0x00000900 /* Decrementer */
67 #define PPC32_EXC_SYSCALL 0x00000C00 /* System Call */
68 #define PPC32_EXC_TRACE 0x00000D00 /* Trace */
69 #define PPC32_EXC_FPU_HLP 0x00000E00 /* Floating-Point Assist */
70
71 /* CR0 (Condition Register Field 0) bits */
72 #define PPC32_CR0_LT_BIT 31
73 #define PPC32_CR0_LT (1 << PPC32_CR0_LT_BIT) /* Negative */
74 #define PPC32_CR0_GT_BIT 30
75 #define PPC32_CR0_GT (1 << PPC32_CR0_GT_BIT) /* Positive */
76 #define PPC32_CR0_EQ_BIT 29
77 #define PPC32_CR0_EQ (1 << PPC32_CR0_EQ_BIT) /* Zero */
78 #define PPC32_CR0_SO_BIT 28
79 #define PPC32_CR0_SO (1 << PPC32_CR0_SO_BIT) /* Summary overflow */
80
81 /* XER register */
82 #define PPC32_XER_SO_BIT 31
83 #define PPC32_XER_SO (1 << PPC32_XER_SO_BIT) /* Summary Overflow */
84 #define PPC32_XER_OV 0x40000000 /* Overflow */
85 #define PPC32_XER_CA_BIT 29
86 #define PPC32_XER_CA (1 << PPC32_XER_CA_BIT) /* Carry */
87 #define PPC32_XER_BC_MASK 0x0000007F /* Byte cnt (lswx/stswx) */
88
89 /* MSR (Machine State Register) */
90 #define PPC32_MSR_POW_MASK 0x00060000 /* Power Management */
91 #define PPC32_MSR_ILE 0x00010000 /* Exception Little-Endian Mode */
92 #define PPC32_MSR_EE 0x00008000 /* External Interrupt Enable */
93 #define PPC32_MSR_PR 0x00004000 /* Privilege Level (0=supervisor) */
94 #define PPC32_MSR_PR_SHIFT 14
95 #define PPC32_MSR_FP 0x00002000 /* Floating-Point Available */
96 #define PPC32_MSR_ME 0x00001000 /* Machine Check Enable */
97 #define PPC32_MSR_FE0 0x00000800 /* Floating-Point Exception Mode 0 */
98 #define PPC32_MSR_SE 0x00000400 /* Single-step trace enable */
99 #define PPC32_MSR_BE 0x00000200 /* Branch Trace Enable */
100 #define PPC32_MSR_FE1 0x00000100 /* Floating-Point Exception Mode 1 */
101 #define PPC32_MSR_IP 0x00000040 /* Exception Prefix */
102 #define PPC32_MSR_IR 0x00000020 /* Instruction address translation */
103 #define PPC32_MSR_DR 0x00000010 /* Data address translation */
104 #define PPC32_MSR_RI 0x00000002 /* Recoverable Exception */
105 #define PPC32_MSR_LE 0x00000001 /* Little-Endian mode enable */
106
107 #define PPC32_RFI_MSR_MASK 0x87c0ff73
108 #define PPC32_EXC_SRR1_MASK 0x0000ff73
109 #define PPC32_EXC_MSR_MASK 0x0006ef32
110
111 /* Number of BAT registers (8 for PowerPC 7448) */
112 #define PPC32_BAT_NR 8
113
114 /* Number of segment registers */
115 #define PPC32_SR_NR 16
116
117 /* Upper BAT register */
118 #define PPC32_UBAT_BEPI_MASK 0xFFFE0000 /* Block Effective Page Index */
119 #define PPC32_UBAT_BEPI_SHIFT 17
120 #define PPC32_UBAT_BL_MASK 0x00001FFC /* Block Length */
121 #define PPC32_UBAT_BL_SHIFT 2
122 #define PPC32_UBAT_XBL_MASK 0x0001FFFC /* Block Length */
123 #define PPC32_UBAT_XBL_SHIFT 2
124 #define PPC32_UBAT_VS 0x00000002 /* Supervisor mode valid bit */
125 #define PPC32_UBAT_VP 0x00000001 /* User mode valid bit */
126 #define PPC32_UBAT_PROT_MASK (PPC32_UBAT_VS|PPC32_UBAT_VP)
127
128 /* Lower BAT register */
129 #define PPC32_LBAT_BRPN_MASK 0xFFFE0000 /* Physical address */
130 #define PPC32_LBAT_BRPN_SHIFT 17
131 #define PPC32_LBAT_WIMG_MASK 0x00000078 /* Memory/cache access mode bits */
132 #define PPC32_LBAT_PP_MASK 0x00000003 /* Protection bits */
133
134 #define PPC32_BAT_ADDR_SHIFT 17
135
136 /* Segment Descriptor */
137 #define PPC32_SD_T 0x80000000
138 #define PPC32_SD_KS 0x40000000 /* Supervisor-state protection key */
139 #define PPC32_SD_KP 0x20000000 /* User-state protection key */
140 #define PPC32_SD_N 0x10000000 /* No-execute protection bit */
141 #define PPC32_SD_VSID_MASK 0x00FFFFFF /* Virtual Segment ID */
142
143 /* SDR1 Register */
144 #define PPC32_SDR1_HTABORG_MASK 0xFFFF0000 /* Physical base address */
145 #define PPC32_SDR1_HTABEXT_MASK 0x0000E000 /* Extended base address */
146 #define PPC32_SDR1_HTABMASK 0x000001FF /* Mask for page table address */
147 #define PPC32_SDR1_HTMEXT_MASK 0x00001FFF /* Extended mask */
148
149 /* Page Table Entry (PTE) size: 64-bits */
150 #define PPC32_PTE_SIZE 8
151
152 /* PTE entry (Up and Lo) */
153 #define PPC32_PTEU_V 0x80000000 /* Valid entry */
154 #define PPC32_PTEU_VSID_MASK 0x7FFFFF80 /* Virtual Segment ID */
155 #define PPC32_PTEU_VSID_SHIFT 7
156 #define PPC32_PTEU_H 0x00000040 /* Hash function */
157 #define PPC32_PTEU_API_MASK 0x0000003F /* Abbreviated Page index */
158 #define PPC32_PTEL_RPN_MASK 0xFFFFF000 /* Physical Page Number */
159 #define PPC32_PTEL_XPN_MASK 0x00000C00 /* Extended Page Number (0-2) */
160 #define PPC32_PTEL_XPN_SHIFT 9
161 #define PPC32_PTEL_R 0x00000100 /* Referenced bit */
162 #define PPC32_PTEL_C 0x00000080 /* Changed bit */
163 #define PPC32_PTEL_WIMG_MASK 0x00000078 /* Mem/cache access mode bits */
164 #define PPC32_PTEL_WIMG_SHIFT 3
165 #define PPC32_PTEL_X_MASK 0x00000004 /* Extended Page Number (3) */
166 #define PPC32_PTEL_X_SHIFT 2
167 #define PPC32_PTEL_PP_MASK 0x00000003 /* Page Protection bits */
168
169 /* DSISR register */
170 #define PPC32_DSISR_NOTRANS 0x40000000 /* No valid translation */
171 #define PPC32_DSISR_STORE 0x02000000 /* Store operation */
172
173 /* PowerPC 405 TLB definitions */
174 #define PPC405_TLBHI_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
175 #define PPC405_TLBHI_SIZE_MASK 0x00000380 /* Page Size */
176 #define PPC405_TLBHI_SIZE_SHIFT 7
177 #define PPC405_TLBHI_V 0x00000040 /* Valid TLB entry */
178 #define PPC405_TLBHI_E 0x00000020 /* Endianness */
179 #define PPC405_TLBHI_U0 0x00000010 /* User-Defined Attribute */
180
181 #define PPC405_TLBLO_RPN_MASK 0xFFFFFC00 /* Real Page Number */
182 #define PPC405_TLBLO_EX 0x00000200 /* Execute Enable */
183 #define PPC405_TLBLO_WR 0x00000100 /* Write Enable */
184 #define PPC405_TLBLO_ZSEL_MASK 0x000000F0 /* Zone Select */
185 #define PPC405_TLBLO_ZSEL_SHIFT 4
186 #define PPC405_TLBLO_W 0x00000008 /* Write-Through */
187 #define PPC405_TLBLO_I 0x00000004 /* Caching Inhibited */
188 #define PPC405_TLBLO_M 0x00000002 /* Memory Coherent */
189 #define PPC405_TLBLO_G 0x00000001 /* Guarded */
190
191 /* Number of TLB entries for PPC405 */
192 #define PPC405_TLB_ENTRIES 64
193
194 struct ppc405_tlb_entry {
195 m_uint32_t tlb_hi,tlb_lo,tid;
196 };
197
198 /* Memory operations */
199 enum {
200 PPC_MEMOP_LOOKUP = 0,
201
202 /* Instruction fetch operation */
203 PPC_MEMOP_IFETCH,
204
205 /* Load operations */
206 PPC_MEMOP_LBZ,
207 PPC_MEMOP_LHZ,
208 PPC_MEMOP_LWZ,
209
210 /* Load operation with sign-extend */
211 PPC_MEMOP_LHA,
212
213 /* Store operations */
214 PPC_MEMOP_STB,
215 PPC_MEMOP_STH,
216 PPC_MEMOP_STW,
217
218 /* Byte-Reversed operations */
219 PPC_MEMOP_LWBR,
220 PPC_MEMOP_STWBR,
221
222 /* String operations */
223 PPC_MEMOP_LSW,
224 PPC_MEMOP_STSW,
225
226 /* FPU operations */
227 PPC_MEMOP_LFD,
228 PPC_MEMOP_STFD,
229
230 /* ICBI - Instruction Cache Block Invalidate */
231 PPC_MEMOP_ICBI,
232
233 PPC_MEMOP_MAX,
234 };
235
236 /* PowerPC CPU type */
237 typedef struct cpu_ppc cpu_ppc_t;
238
239 /* Memory operation function prototype */
240 typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
241 u_int reg);
242
243 /* BAT type indexes */
244 enum {
245 PPC32_IBAT_IDX = 0,
246 PPC32_DBAT_IDX,
247 };
248
249 /* BAT register */
250 struct ppc32_bat_reg {
251 m_uint32_t reg[2];
252 };
253
254 /* BAT register programming */
255 struct ppc32_bat_prog {
256 int type,index;
257 m_uint32_t hi,lo;
258 };
259
260 /* MTS Instruction Cache and Data Cache */
261 #define PPC32_MTS_ICACHE PPC32_IBAT_IDX
262 #define PPC32_MTS_DCACHE PPC32_DBAT_IDX
263
264 /* FPU Coprocessor definition */
265 typedef struct {
266 m_uint64_t reg[PPC32_FPU_REG_NR];
267 }ppc_fpu_t;
268
269 /* Maximum number of breakpoints */
270 #define PPC32_MAX_BREAKPOINTS 8
271
272 /* PowerPC CPU definition */
273 struct cpu_ppc {
274 /* Instruction address */
275 m_uint32_t ia;
276
277 /* General Purpose registers */
278 m_uint32_t gpr[PPC32_GPR_NR];
279
280 /* Pending IRQ */
281 volatile m_uint32_t irq_pending,irq_check;
282
283 /* XER, Condition Register, Link Register, Count Register */
284 m_uint32_t xer,cr,lr,ctr,reserve;
285 m_uint32_t xer_ca;
286
287 /* MTS caches (Instruction+Data) */
288 mts32_entry_t *mts_cache[2];
289
290 /* Code page translation cache */
291 ppc32_jit_tcb_t **exec_phys_map;
292
293 /* Virtual address to physical page translation */
294 fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
295 m_uint32_t *phys_page);
296
297 /* Memory access functions */
298 ppc_memop_fn mem_op_fn[PPC_MEMOP_MAX];
299
300 /* Memory lookup function (to load ELF image,...) */
301 void *(*mem_op_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid);
302
303 /* MTS slow lookup function */
304 mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
305 u_int cid,u_int op_code,u_int op_size,
306 u_int op_type,m_uint64_t *data,
307 u_int *exc,mts32_entry_t *alt_entry);
308
309 /* IRQ counters */
310 m_uint64_t irq_count,timer_irq_count,irq_fp_count;
311 pthread_mutex_t irq_lock;
312
313 /* Current and free lists of translated code blocks */
314 ppc32_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list;
315
316 /* Executable page area */
317 void *exec_page_area;
318 size_t exec_page_area_size;
319 size_t exec_page_count,exec_page_alloc;
320 insn_exec_page_t *exec_page_free_list;
321 insn_exec_page_t *exec_page_array;
322
323 /* Idle PC value */
324 volatile m_uint32_t idle_pc;
325
326 /* Timer IRQs */
327 volatile u_int timer_irq_pending,timer_irq_armed;
328 u_int timer_irq_freq;
329 u_int timer_irq_check_itv;
330 u_int timer_drift;
331
332 /* IRQ disable flag */
333 volatile u_int irq_disable;
334
335 /* IBAT (Instruction) and DBAT (Data) registers */
336 struct ppc32_bat_reg bat[2][PPC32_BAT_NR];
337
338 /* Segment registers */
339 m_uint32_t sr[PPC32_SR_NR];
340
341 /* Page Table Address */
342 m_uint32_t sdr1;
343 void *sdr1_hptr;
344
345 /* MSR (Machine state register) */
346 m_uint32_t msr;
347
348 /* Interrupt Registers (SRR0/SRR1) */
349 m_uint32_t srr0,srr1,dsisr,dar;
350
351 /* SPRG registers */
352 m_uint32_t sprg[4];
353
354 /* PVR (Processor Version Register) */
355 m_uint32_t pvr;
356
357 /* Time-Base register */
358 m_uint64_t tb;
359
360 /* Decrementer */
361 m_uint32_t dec;
362
363 /* Hardware Implementation Dependent Registers */
364 m_uint32_t hid0,hid1;
365
366 /* String instruction position (lswi/stswi) */
367 u_int sw_pos;
368
369 /* PowerPC 405 TLB */
370 struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
371 m_uint32_t ppc405_pid;
372
373 /* FPU */
374 ppc_fpu_t fpu;
375
376 /* Generic CPU instance pointer */
377 cpu_gen_t *gen;
378
379 /* VM instance */
380 vm_instance_t *vm;
381
382 /* MTS cache statistics */
383 m_uint64_t mts_misses,mts_lookups;
384
385 /* JIT flush method */
386 u_int jit_flush_method;
387
388 /* Number of compiled pages */
389 u_int compiled_pages;
390
391 /* Fast memory operations use */
392 u_int fast_memop;
393
394 /* IRQ idling preemption */
395 u_int irq_idle_preempt[32];
396
397 /* Current exec page (non-JIT) info */
398 m_uint64_t njm_exec_page;
399 mips_insn_t *njm_exec_ptr;
400
401 /* Performance counter (non-JIT) */
402 m_uint64_t perf_counter;
403
404 /* non-JIT mode instruction counter */
405 m_uint64_t insn_exec_count;
406
407 /* Breakpoints */
408 m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
409 u_int breakpoints_enabled;
410 };
411
412 /* Reset a PowerPC CPU */
413 int ppc32_reset(cpu_ppc_t *cpu);
414
415 /* Initialize a PowerPC processor */
416 int ppc32_init(cpu_ppc_t *cpu);
417
418 /* Delete a PowerPC processor */
419 void ppc32_delete(cpu_ppc_t *cpu);
420
421 /* Set the processor version register (PVR) */
422 void ppc32_set_pvr(cpu_ppc_t *cpu,m_uint32_t pvr);
423
424 /* Set idle PC value */
425 void ppc32_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr);
426
427 /* Timer IRQ */
428 void *ppc32_timer_irq_run(cpu_ppc_t *cpu);
429
430 /* Determine an "idling" PC */
431 int ppc32_get_idling_pc(cpu_gen_t *cpu);
432
433 /* Generate an exception */
434 void ppc32_trigger_exception(cpu_ppc_t *cpu,u_int exc_vector);
435
436 /* Trigger the decrementer exception */
437 void ppc32_trigger_timer_irq(cpu_ppc_t *cpu);
438
439 /* Trigger IRQs */
440 fastcall void ppc32_trigger_irq(cpu_ppc_t *cpu);
441
442 /* Virtual breakpoint */
443 fastcall void ppc32_run_breakpoint(cpu_ppc_t *cpu);
444
445 /* Add a virtual breakpoint */
446 int ppc32_add_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);
447
448 /* Remove a virtual breakpoint */
449 void ppc32_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);
450
451 /* Set a register */
452 void ppc32_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val);
453
454 /* Dump registers of a PowerPC processor */
455 void ppc32_dump_regs(cpu_gen_t *cpu);
456
457 /* Dump MMU registers */
458 void ppc32_dump_mmu(cpu_gen_t *cpu);
459
460 /* Load a raw image into the simulated memory */
461 int ppc32_load_raw_image(cpu_ppc_t *cpu,char *filename,m_uint32_t vaddr);
462
463 /* Load an ELF image into the simulated memory */
464 int ppc32_load_elf_image(cpu_ppc_t *cpu,char *filename,int skip_load,
465 m_uint32_t *entry_point);
466
467 /* Run PowerPC code in step-by-step mode */
468 void *ppc32_exec_run_cpu(cpu_gen_t *gen);
469
470 #endif

  ViewVC Help
Powered by ViewVC 1.1.26