upstream/dynamips-0.2.7-RC2/mips64_nojit_trans.h

/*
 * Cisco router simulation platform.
 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
 *
 * Just an empty JIT template file for architectures not supported by the JIT
 * code.
 */

#ifndef __MIPS64_NOJIT_TRANS_H__
#define __MIPS64_NOJIT_TRANS_H__

#include "utils.h"
#include "cpu.h"
#include "dynamips.h"

#define JIT_SUPPORT 0

#define mips64_jit_tcb_set_patch(a,b)
#define mips64_jit_tcb_set_jump(a,b)

/* MIPS instruction array */
extern struct mips64_insn_tag mips64_insn_tags[];

/* Push epilog for an x86 instruction block */
void mips64_jit_tcb_push_epilog(mips64_jit_tcb_t *block);

/* Execute JIT code */
void mips64_jit_tcb_exec(cpu_mips_t *cpu,mips64_jit_tcb_t *block);

/* Set the Pointer Counter (PC) register */
void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc);

/* Set the Return Address (RA) register */
void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc);

/* Virtual Breakpoint */
void mips64_emit_breakpoint(mips64_jit_tcb_t *b);

/* Emit unhandled instruction code */
void mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b);

/* 
 * Increment count register and trigger the timer IRQ if value in compare 
 * register is the same.
 */
void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b);

/* Increment the number of executed instructions (performance debugging) */
void mips64_inc_perf_counter(mips64_jit_tcb_t *b);

#endif
1	dpavlin	7	/*
2			* Cisco router simulation platform.
3			* Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4			*
5			* Just an empty JIT template file for architectures not supported by the JIT
6			* code.
7			*/
8
9			#ifndef __MIPS64_NOJIT_TRANS_H__
10			#define __MIPS64_NOJIT_TRANS_H__
11
12			#include "utils.h"
13			#include "cpu.h"
14			#include "dynamips.h"
15
16			#define JIT_SUPPORT 0
17
18			#define mips64_jit_tcb_set_patch(a,b)
19			#define mips64_jit_tcb_set_jump(a,b)
20
21			/* MIPS instruction array */
22			extern struct mips64_insn_tag mips64_insn_tags[];
23
24			/* Push epilog for an x86 instruction block */
25			void mips64_jit_tcb_push_epilog(mips64_jit_tcb_t *block);
26
27			/* Execute JIT code */
28			void mips64_jit_tcb_exec(cpu_mips_t cpu,mips64_jit_tcb_t block);
29
30			/* Set the Pointer Counter (PC) register */
31			void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc);
32
33			/* Set the Return Address (RA) register */
34			void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc);
35
36			/* Virtual Breakpoint */
37			void mips64_emit_breakpoint(mips64_jit_tcb_t *b);
38
39			/* Emit unhandled instruction code */
40			void mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b);
41
42			/*
43			* Increment count register and trigger the timer IRQ if value in compare
44			* register is the same.
45			*/
46			void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b);
47
48			/* Increment the number of executed instructions (performance debugging) */
49			void mips64_inc_perf_counter(mips64_jit_tcb_t *b);
50
51			#endif