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dpavlin |
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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#ifndef __CP0_H__ |
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#define __CP0_H__ |
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#include "utils.h" |
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/* CP0 register names */ |
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extern char *mips64_cp0_reg_names[]; |
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/* Get cp0 register index given its name */ |
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int mips64_cp0_get_reg_index(char *name); |
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/* Get the CPU operating mode (User,Supervisor or Kernel) */ |
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u_int mips64_cp0_get_mode(cpu_mips_t *cpu); |
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/* Get a cp0 register */ |
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m_uint64_t mips64_cp0_get_reg(cpu_mips_t *cpu,u_int cp0_reg); |
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/* DMFC0 */ |
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fastcall void mips64_cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg, |
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u_int cp0_reg); |
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/* DMTC0 */ |
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fastcall void mips64_cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg, |
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u_int cp0_reg); |
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/* MFC0 */ |
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fastcall void mips64_cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg); |
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/* MTC0 */ |
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fastcall void mips64_cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg); |
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/* CFC0 */ |
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fastcall void mips64_cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg); |
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/* CTC0 */ |
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fastcall void mips64_cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg); |
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/* TLB lookup */ |
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int mips64_cp0_tlb_lookup(cpu_mips_t *cpu,m_uint64_t vaddr,mts_map_t *res); |
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/* Map all TLB entries into the MTS */ |
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void mips64_cp0_map_all_tlb_to_mts(cpu_mips_t *cpu); |
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/* TLBP: Probe a TLB entry */ |
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fastcall void mips64_cp0_exec_tlbp(cpu_mips_t *cpu); |
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/* TLBR: Read Indexed TLB entry */ |
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fastcall void mips64_cp0_exec_tlbr(cpu_mips_t *cpu); |
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/* TLBWI: Write Indexed TLB entry */ |
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fastcall void mips64_cp0_exec_tlbwi(cpu_mips_t *cpu); |
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/* TLBWR: Write Random TLB entry */ |
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fastcall void mips64_cp0_exec_tlbwr(cpu_mips_t *cpu); |
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/* Raw dump of the TLB */ |
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void mips64_tlb_raw_dump(cpu_gen_t *cpu); |
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/* Dump the specified TLB entry */ |
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void mips64_tlb_dump_entry(cpu_mips_t *cpu,u_int index); |
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/* Human-Readable dump of the TLB */ |
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void mips64_tlb_dump(cpu_gen_t *cpu); |
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#endif |