/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_sb1_pci.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /upstream/dynamips-0.2.7-RC2/dev_sb1_pci.c

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upstream/dynamips-0.2.6-RC5/dev_sb1_pci.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_sb1_pci.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (c) 2006 Christophe Fillot.  All rights reserved.   * Copyright (c) 2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * PCI configuration space for SB-1 processor.   * PCI configuration space for SB-1 processor.
# Line 11  Line 11 
11  #include <time.h>  #include <time.h>
12  #include <errno.h>  #include <errno.h>
13    
14  #include "mips64.h"  #include "cpu.h"
15    #include "vm.h"
16  #include "dynamips.h"  #include "dynamips.h"
17  #include "memory.h"  #include "memory.h"
18  #include "device.h"  #include "device.h"
# Line 39  struct sb1_pci_data { Line 40  struct sb1_pci_data {
40   *   *
41   * PCI Configuration (Bus 0, Device 0).   * PCI Configuration (Bus 0, Device 0).
42   */   */
43  static m_uint32_t sb1_pci_cfg_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t sb1_pci_cfg_read(cpu_gen_t *cpu,struct pci_device *dev,
44                                     int reg)                                     int reg)
45  {  {
46     switch(reg) {     switch(reg) {
# Line 55  static m_uint32_t sb1_pci_cfg_read(cpu_m Line 56  static m_uint32_t sb1_pci_cfg_read(cpu_m
56   *   *
57   * HyperTransport Configuration (Bus 0, Device 1).   * HyperTransport Configuration (Bus 0, Device 1).
58   */   */
59  static m_uint32_t sb1_ht_cfg_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t sb1_ht_cfg_read(cpu_gen_t *cpu,struct pci_device *dev,
60                                    int reg)                                    int reg)
61  {  {
62     switch(reg) {     switch(reg) {
# Line 71  static m_uint32_t sb1_ht_cfg_read(cpu_mi Line 72  static m_uint32_t sb1_ht_cfg_read(cpu_mi
72  /*  /*
73   * dev_sb1_pci_access()   * dev_sb1_pci_access()
74   */   */
75  void *dev_sb1_pci_access(cpu_mips_t *cpu,struct vdevice *dev,  void *dev_sb1_pci_access(cpu_gen_t *cpu,struct vdevice *dev,
76                           m_uint32_t offset,u_int op_size,u_int op_type,                           m_uint32_t offset,u_int op_size,u_int op_type,
77                           m_uint64_t *data)                           m_uint64_t *data)
78  {  {
# Line 80  void *dev_sb1_pci_access(cpu_mips_t *cpu Line 81  void *dev_sb1_pci_access(cpu_mips_t *cpu
81  #if DEBUG_ACCESS  #if DEBUG_ACCESS
82     if (op_type == MTS_READ)     if (op_type == MTS_READ)
83        cpu_log(cpu,dev->name,"read  access to offset = 0x%x, pc = 0x%llx\n",        cpu_log(cpu,dev->name,"read  access to offset = 0x%x, pc = 0x%llx\n",
84                offset,cpu->pc);                offset,cpu_get_pc(cpu));
85     else     else
86        cpu_log(cpu,dev->name,"write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,dev->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
87                "val = 0x%llx\n",offset,cpu->pc,*data);                "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
88  #endif  #endif
89    
90     if (op_type == MTS_READ)     if (op_type == MTS_READ)

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