/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_c7200_mpfpga.c
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Diff of /upstream/dynamips-0.2.7-RC2/dev_c7200_mpfpga.c

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upstream/dynamips-0.2.6-RC5/dev_c7200_mpfpga.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c7200_mpfpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Cisco C7200 (Predator) Midplane FPGA.   * Cisco c7200 Midplane FPGA.
6   */   */
7    
8  #include <stdio.h>  #include <stdio.h>
9  #include <stdlib.h>  #include <stdlib.h>
10  #include <string.h>  #include <string.h>
11    
12  #include "mips64.h"  #include "cpu.h"
13    #include "vm.h"
14  #include "dynamips.h"  #include "dynamips.h"
15  #include "memory.h"  #include "memory.h"
16  #include "device.h"  #include "device.h"
# Line 18  Line 19 
19    
20  #define DEBUG_UNKNOWN  1  #define DEBUG_UNKNOWN  1
21  #define DEBUG_ACCESS   0  #define DEBUG_ACCESS   0
22  #define DEBUG_OIR      0  #define DEBUG_OIR      1
23    
24  /*  /*
25   * Definitions for Port Adapter Status.   * Definitions for Port Adapter Status.
# Line 156  static void pa_update_status_reg(struct Line 157  static void pa_update_status_reg(struct
157    
158     /* PA Power. Bay 0 is always powered */     /* PA Power. Bay 0 is always powered */
159     res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK;     res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK;
160      
161     /* We fake power on bays defined by the final user */     /* We fake power on bays defined by the final user */
162     if (c7200_pa_check_eeprom(d->router,1))     if (c7200_pa_check_eeprom(d->router,1))
163        res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK;        res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK;
# Line 182  static void pa_update_status_reg(struct Line 183  static void pa_update_status_reg(struct
183  /*  /*
184   * dev_mpfpga_access()   * dev_mpfpga_access()
185   */   */
186  void *dev_c7200_mpfpga_access(cpu_mips_t *cpu,struct vdevice *dev,  void *dev_c7200_mpfpga_access(cpu_gen_t *cpu,struct vdevice *dev,
187                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
188                                m_uint64_t *data)                                m_uint64_t *data)
189  {  {
# Line 198  void *dev_c7200_mpfpga_access(cpu_mips_t Line 199  void *dev_c7200_mpfpga_access(cpu_mips_t
199  #if DEBUG_ACCESS  #if DEBUG_ACCESS
200     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
201        cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",        cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
202                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
203     } else {     } else {
204        cpu_log(cpu,"MP_FPGA",        cpu_log(cpu,"MP_FPGA",
205                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
206                offset,cpu->pc,*data,op_size);                offset,cpu_get_pc(cpu),*data,op_size);
207     }     }
208  #endif  #endif
209    
# Line 239  void *dev_c7200_mpfpga_access(cpu_mips_t Line 240  void *dev_c7200_mpfpga_access(cpu_mips_t
240           if (op_type == MTS_READ)           if (op_type == MTS_READ)
241              *data = 0x66666600 & d->pa_status_reg;              *data = 0x66666600 & d->pa_status_reg;
242    
243           mips64_clear_irq(cpu,C7200_PA_MGMT_IRQ);           vm_clear_irq(d->router->vm,C7200_PA_MGMT_IRQ);
244           break;           break;
245    
246        case 0x48:  /* ??? (test) */        case 0x48:  /* ??? (test) */
# Line 258  void *dev_c7200_mpfpga_access(cpu_mips_t Line 259  void *dev_c7200_mpfpga_access(cpu_mips_t
259           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
260  #if DEBUG_OIR  #if DEBUG_OIR
261              cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n",              cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n",
262                      offset,cpu->pc,d->router->oir_status);                      offset,cpu_get_pc(cpu),d->router->oir_status);
263  #endif  #endif
264              *data = d->router->oir_status;              *data = d->router->oir_status;
265                vm_clear_irq(d->router->vm,C7200_OIR_IRQ);
266           } else {           } else {
267  #if DEBUG_OIR  #if DEBUG_OIR
268              cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx "              cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx "
269                      "(data=0x%llx)\n",offset,cpu->pc,*data);                      "(data=0x%llx)\n",offset,cpu_get_pc(cpu),*data);
270  #endif  #endif
271              d->router->oir_status &= ~(*data);              d->router->oir_status &= ~(*data);
272              vm_clear_irq(d->router->vm,C7200_OIR_IRQ);                                  vm_clear_irq(d->router->vm,C7200_OIR_IRQ);                    
# Line 278  void *dev_c7200_mpfpga_access(cpu_mips_t Line 280  void *dev_c7200_mpfpga_access(cpu_mips_t
280        case 0x78:        case 0x78:
281           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
282  #if DEBUG_OIR  #if DEBUG_OIR
283              cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",cpu->pc);              cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",
284                        cpu_get_pc(cpu));
285  #endif  #endif
286              *data = 0x00;              *data = 0x00;
287           } else {           } else {
288  #if DEBUG_OIR  #if DEBUG_OIR
289              cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx "              cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx "
290                    "(data=0x%llx)\n",cpu->pc,*data);                    "(data=0x%llx)\n",cpu_get_pc(cpu),*data);
291  #endif  #endif
292           }           }
293           break;           break;
# Line 327  void *dev_c7200_mpfpga_access(cpu_mips_t Line 330  void *dev_c7200_mpfpga_access(cpu_mips_t
330        default:        default:
331           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
332              cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n",
333                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
334           } else {           } else {
335              cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, "
336                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
337           }           }
338  #endif  #endif
339     }     }

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