/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_c7200_iofpga.c
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Contents of /upstream/dynamips-0.2.7-RC2/dev_c7200_iofpga.c

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Revision 8 - (show annotations)
Sat Oct 6 16:24:54 2007 UTC (12 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 20798 byte(s)
dynamips-0.2.7-RC2

1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4 *
5 * Cisco 7200 I/O FPGA:
6 * - Simulates a NMC93C46 Serial EEPROM as CPU and Midplane EEPROM.
7 * - Simulates a DALLAS DS1620 for Temperature Sensors.
8 * - Simulates voltage sensors.
9 * - Simulates console and AUX ports (SCN2681).
10 */
11
12 #include <stdio.h>
13 #include <stdlib.h>
14 #include <string.h>
15 #include <unistd.h>
16 #include <sys/types.h>
17
18 #include <termios.h>
19 #include <fcntl.h>
20 #include <pthread.h>
21
22 #include "ptask.h"
23 #include "cpu.h"
24 #include "vm.h"
25 #include "dynamips.h"
26 #include "memory.h"
27 #include "device.h"
28 #include "dev_vtty.h"
29 #include "nmc93cX6.h"
30 #include "ds1620.h"
31 #include "dev_c7200.h"
32
33 /* Debugging flags */
34 #define DEBUG_UNKNOWN 1
35 #define DEBUG_ACCESS 0
36 #define DEBUG_LED 0
37 #define DEBUG_IO_CTL 0
38 #define DEBUG_ENVM 0
39
40 /* DUART RX/TX status (SRA/SRB) */
41 #define DUART_RX_READY 0x01
42 #define DUART_TX_READY 0x04
43
44 /* DUART RX/TX Interrupt Status/Mask */
45 #define DUART_TXRDYA 0x01
46 #define DUART_RXRDYA 0x02
47 #define DUART_TXRDYB 0x10
48 #define DUART_RXRDYB 0x20
49
50 /* Definitions for CPU and Midplane Serial EEPROMs */
51 #define DO2_DATA_OUT_MIDPLANE 7
52 #define DO1_DATA_OUT_CPU 6
53 #define CS2_CHIP_SEL_MIDPLANE 5
54 #define SK2_CLOCK_MIDPLANE 4
55 #define DI2_DATA_IN_MIDPLANE 3
56 #define CS1_CHIP_SEL_CPU 2
57 #define SK1_CLOCK_CPU 1
58 #define DI1_DATA_IN_CPU 0
59
60 /* Definitions for PEM (NPE-B) Serial EEPROM */
61 #define DO1_DATA_OUT_PEM 3
62 #define DI1_DATA_IN_PEM 2
63 #define CS1_CHIP_SEL_PEM 1
64 #define SK1_CLOCK_PEM 0
65
66 /* Pack the NVRAM */
67 #define NVRAM_PACKED 0x04
68
69 /* 4 temperature sensors in a C7200 */
70 #define C7200_TEMP_SENSORS 4
71 #define C7200_DEFAULT_TEMP 22 /* default temperature: 22°C */
72
73 /* Voltages */
74 #define C7200_A2D_SAMPLES 9
75
76 /*
77 * A2D MUX Select definitions.
78 */
79 #define C7200_MUX_PS0 0x00 /* Power Supply 0 */
80 #define C7200_MUX_PS1 0x02 /* Power Supply 1 */
81 #define C7200_MUX_P3V 0x04 /* +3V */
82 #define C7200_MUX_P12V 0x08 /* +12V */
83 #define C7200_MUX_P5V 0x0a /* +5V */
84 #define C7200_MUX_N12V 0x0c /* -12V */
85
86 /* Analog To Digital Converters samples */
87 #define C7200_A2D_PS0 1150
88 #define C7200_A2D_PS1 1150
89
90 /* Voltage Samples */
91 #define C7200_A2D_P3V 1150
92 #define C7200_A2D_P12V 1150
93 #define C7200_A2D_P5V 1150
94 #define C7200_A2D_N12V 1150
95
96 /* IO FPGA structure */
97 struct iofpga_data {
98 vm_obj_t vm_obj;
99 struct vdevice dev;
100 c7200_t *router;
101
102 /* Lock test */
103 pthread_mutex_t lock;
104
105 /* Periodic task to trigger dummy DUART IRQ */
106 ptask_id_t duart_irq_tid;
107
108 /* DUART & Console Management */
109 u_int duart_isr,duart_imr,duart_irq_seq;
110
111 /* IO control register */
112 u_int io_ctrl_reg;
113
114 /* Temperature Control */
115 u_int temp_cfg_reg[C7200_TEMP_SENSORS];
116 u_int temp_deg_reg[C7200_TEMP_SENSORS];
117 u_int temp_clk_low;
118
119 u_int temp_cmd;
120 u_int temp_cmd_pos;
121
122 u_int temp_data;
123 u_int temp_data_pos;
124
125 /* Voltages */
126 u_int mux;
127
128 /* NPE-G2 environmental part */
129 m_uint32_t envm_r0,envm_r1,envm_r2;
130 };
131
132 #define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock)
133 #define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock)
134
135 /* CPU EEPROM definition */
136 static const struct nmc93cX6_eeprom_def eeprom_cpu_def = {
137 SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU,
138 DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU,
139 };
140
141 /* Midplane EEPROM definition */
142 static const struct nmc93cX6_eeprom_def eeprom_midplane_def = {
143 SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE,
144 DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE,
145 };
146
147 /* PEM (NPE-B) EEPROM definition */
148 static const struct nmc93cX6_eeprom_def eeprom_pem_def = {
149 SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM,
150 };
151
152 /* IOFPGA manages simultaneously CPU and Midplane EEPROM */
153 static const struct nmc93cX6_group eeprom_cpu_midplane = {
154 EEPROM_TYPE_NMC93C46, 2, 0, "CPU and Midplane EEPROM", 0,
155 { &eeprom_cpu_def, &eeprom_midplane_def },
156 };
157
158 /*
159 * IOFPGA manages also PEM EEPROM (for NPE-B)
160 * PEM stands for "Power Entry Module":
161 * http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml
162 */
163 static const struct nmc93cX6_group eeprom_pem_npeb = {
164 EEPROM_TYPE_NMC93C46, 1, 0, "PEM (NPE-B) EEPROM", 0, { &eeprom_pem_def },
165 };
166
167 /* Reset DS1620 */
168 static void temp_reset(struct iofpga_data *d)
169 {
170 d->temp_cmd_pos = 0;
171 d->temp_cmd = 0;
172
173 d->temp_data_pos = 0;
174 d->temp_data = 0;
175 }
176
177 /* Write the temperature control data */
178 static void temp_write_ctrl(struct iofpga_data *d,u_char val)
179 {
180 switch(val) {
181 case DS1620_RESET_ON:
182 temp_reset(d);
183 break;
184
185 case DS1620_CLK_LOW:
186 d->temp_clk_low = 1;
187 break;
188
189 case DS1620_CLK_HIGH:
190 d->temp_clk_low = 0;
191 break;
192 }
193 }
194
195 /* Read a temperature control data */
196 static u_int temp_read_data(struct iofpga_data *d)
197 {
198 u_int i,data = 0;
199
200 switch(d->temp_cmd) {
201 case DS1620_READ_CONFIG:
202 for(i=0;i<C7200_TEMP_SENSORS;i++)
203 data |= ((d->temp_cfg_reg[i] >> d->temp_data_pos) & 1) << i;
204
205 d->temp_data_pos++;
206
207 if (d->temp_data_pos == DS1620_CONFIG_READ_SIZE)
208 temp_reset(d);
209
210 break;
211
212 case DS1620_READ_TEMP:
213 for(i=0;i<C7200_TEMP_SENSORS;i++)
214 data |= ((d->temp_deg_reg[i] >> d->temp_data_pos) & 1) << i;
215
216 d->temp_data_pos++;
217
218 if (d->temp_data_pos == DS1620_DATA_READ_SIZE)
219 temp_reset(d);
220
221 break;
222
223 default:
224 vm_log(d->router->vm,"IO_FPGA","temp_sensors: CMD = 0x%x\n",
225 d->temp_cmd);
226 }
227
228 return(data);
229 }
230
231 /* Write the temperature data write register */
232 static void temp_write_data(struct iofpga_data *d,u_char val)
233 {
234 if (val == DS1620_ENABLE_READ) {
235 d->temp_data_pos = 0;
236 return;
237 }
238
239 if (!d->temp_clk_low)
240 return;
241
242 /* Write a command */
243 if (d->temp_cmd_pos < DS1620_WRITE_SIZE)
244 {
245 if (val == DS1620_DATA_HIGH)
246 d->temp_cmd |= 1 << d->temp_cmd_pos;
247
248 d->temp_cmd_pos++;
249
250 if (d->temp_cmd_pos == DS1620_WRITE_SIZE) {
251 switch(d->temp_cmd) {
252 case DS1620_START_CONVT:
253 //printf("temp_sensors: IOS enabled continuous monitoring.\n");
254 temp_reset(d);
255 break;
256 case DS1620_READ_CONFIG:
257 case DS1620_READ_TEMP:
258 break;
259 default:
260 vm_log(d->router->vm,"IO_FPGA",
261 "temp_sensors: IOS sent command 0x%x.\n",
262 d->temp_cmd);
263 }
264 }
265 }
266 else
267 {
268 if (val == DS1620_DATA_HIGH)
269 d->temp_data |= 1 << d->temp_data_pos;
270
271 d->temp_data_pos++;
272 }
273 }
274
275 /* NPE-G2 environmental monitor reading */
276 static m_uint32_t g2_envm_read(struct iofpga_data *d)
277 {
278 m_uint32_t val = 0;
279 m_uint32_t p1;
280
281 p1 = ((d->envm_r2 & 0xFF) << 8) | d->envm_r0 >> 3;
282
283 switch(p1) {
284 case 0x2a00: /* CPU Die Temperature */
285 val = 0x3000;
286 break;
287 case 0x4c00: /* +3.30V */
288 val = 0x2a9;
289 break;
290 case 0x4c01: /* +1.50V */
291 val = 0x135;
292 break;
293 case 0x4c02: /* +2.50V */
294 val = 0x204;
295 break;
296 case 0x4c03: /* +1.80V */
297 val = 0x173;
298 break;
299 case 0x4c04: /* +1.20V */
300 val = 0xF7;
301 break;
302 case 0x4c05: /* VDD_CPU */
303 val = 0x108;
304 break;
305 case 0x4800: /* VDD_MEM */
306 val = 0x204;
307 break;
308 case 0x4801: /* VTT */
309 val = 0xF9;
310 break;
311 case 0x4802: /* +3.45V */
312 val = 0x2c8;
313 break;
314 case 0x4803: /* -11.95V*/
315 val = 0x260;
316 break;
317 case 0x4804: /* ? */
318 val = 0x111;
319 break;
320 case 0x4805: /* ? */
321 val = 0x111;
322 break;
323 case 0x4806: /* +5.15V */
324 val = 0x3F8;
325 break;
326 case 0x4807: /* +12.15V */
327 val = 0x33D;
328 break;
329 #if DEBUG_UNKNOWN
330 default:
331 vm_log(d->router->vm,"IO_FPGA","p1 = 0x%8.8x\n",p1);
332 #endif
333 }
334
335 return(htonl(val));
336 }
337
338 /* Console port input */
339 static void tty_con_input(vtty_t *vtty)
340 {
341 struct iofpga_data *d = vtty->priv_data;
342
343 IOFPGA_LOCK(d);
344 if (d->duart_imr & DUART_RXRDYA) {
345 d->duart_isr |= DUART_RXRDYA;
346 vm_set_irq(d->router->vm,C7200_DUART_IRQ);
347 }
348 IOFPGA_UNLOCK(d);
349 }
350
351 /* AUX port input */
352 static void tty_aux_input(vtty_t *vtty)
353 {
354 struct iofpga_data *d = vtty->priv_data;
355
356 IOFPGA_LOCK(d);
357 if (d->duart_imr & DUART_RXRDYB) {
358 d->duart_isr |= DUART_RXRDYB;
359 vm_set_irq(d->router->vm,C7200_DUART_IRQ);
360 }
361 IOFPGA_UNLOCK(d);
362 }
363
364 /* IRQ trickery for Console and AUX ports */
365 static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg)
366 {
367 u_int mask;
368
369 IOFPGA_LOCK(d);
370 d->duart_irq_seq++;
371
372 if (d->duart_irq_seq == 2) {
373 mask = DUART_TXRDYA|DUART_TXRDYB;
374 if (d->duart_imr & mask) {
375 d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB;
376 vm_set_irq(d->router->vm,C7200_DUART_IRQ);
377 }
378
379 d->duart_irq_seq = 0;
380 }
381
382 IOFPGA_UNLOCK(d);
383 return(0);
384 }
385
386 /*
387 * dev_c7200_iofpga_access()
388 */
389 void *dev_c7200_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
390 m_uint32_t offset,u_int op_size,u_int op_type,
391 m_uint64_t *data)
392 {
393 struct iofpga_data *d = dev->priv_data;
394 vm_instance_t *vm = d->router->vm;
395 u_char odata;
396
397 if (op_type == MTS_READ)
398 *data = 0x0;
399
400 #if DEBUG_ACCESS
401 if (op_type == MTS_READ) {
402 cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n",
403 offset,cpu_get_pc(cpu));
404 } else {
405 cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n",
406 offset,cpu_get_pc(cpu),*data);
407 }
408 #endif
409
410 IOFPGA_LOCK(d);
411
412 switch(offset) {
413 case 0x294:
414 /*
415 * Unknown, seen in 12.4(6)T, and seems to be read at each
416 * network interrupt.
417 */
418 if (op_type == MTS_READ)
419 *data = 0x0;
420 break;
421
422 /* NPE-G1 test - unknown (value written: 0x01) */
423 case 0x338:
424 break;
425
426 /*
427 * NPE-G1/NPE-G2 - has influence on slot 0 / flash / pcmcia ...
428 * Bit 24: 1=I/O slot present
429 * Lower 16 bits: FPGA version (displayed by "sh c7200")
430 */
431 case 0x390:
432 if (op_type == MTS_READ) {
433 *data = 0x0102;
434
435 /* If we have an I/O slot, we use the I/O slot DUART */
436 if (c7200_pa_check_eeprom(d->router,0))
437 *data |= 0x01000000;
438 }
439 break;
440
441 /* I/O control register */
442 case 0x204:
443 if (op_type == MTS_WRITE) {
444 #if DEBUG_IO_CTL
445 vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data);
446 #endif
447 d->io_ctrl_reg = *data;
448 } else {
449 *data = d->io_ctrl_reg;
450 *data |= NVRAM_PACKED; /* Packed NVRAM */
451 }
452 break;
453
454 /* CPU/Midplane EEPROMs */
455 case 0x21c:
456 if (op_type == MTS_WRITE)
457 nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data));
458 else
459 *data = nmc93cX6_read(&d->router->sys_eeprom_g1);
460 break;
461
462 /* PEM (NPE-B) EEPROM */
463 case 0x388:
464 if (op_type == MTS_WRITE)
465 nmc93cX6_write(&d->router->sys_eeprom_g2,(u_int)(*data));
466 else
467 *data = nmc93cX6_read(&d->router->sys_eeprom_g2);
468 break;
469
470 /* Watchdog */
471 case 0x234:
472 break;
473
474 /*
475 * FPGA release/presence ? Flash SIMM size:
476 * 0x0001: 2048K Flash (2 banks)
477 * 0x0504: 8192K Flash (2 banks)
478 * 0x0704: 16384K Flash (2 banks)
479 * 0x0904: 32768K Flash (2 banks)
480 * 0x0B04: 65536K Flash (2 banks)
481 * 0x2001: 1024K Flash (1 bank)
482 * 0x2504: 4096K Flash (1 bank)
483 * 0x2704: 8192K Flash (1 bank)
484 * 0x2904: 16384K Flash (1 bank)
485 * 0x2B04: 32768K Flash (1 bank)
486 *
487 * Number of Flash SIMM banks + size.
488 * Touching some lower bits causes problems with environmental monitor.
489 *
490 * It is displayed by command "sh bootflash: chips"
491 */
492 case 0x23c:
493 if (op_type == MTS_READ)
494 *data = 0x2704;
495 break;
496
497 /* LEDs */
498 case 0x244:
499 #if DEBUG_LED
500 vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n",
501 *data,(~*data) & 0x0F);
502 #endif
503 break;
504
505 /* ==== DUART SCN2681 (console/aux) ==== */
506 case 0x404: /* Mode Register A (MRA) */
507 break;
508
509 case 0x40c: /* Status Register A (SRA) */
510 if (op_type == MTS_READ) {
511 odata = 0;
512
513 if (vtty_is_char_avail(vm->vtty_con))
514 odata |= DUART_RX_READY;
515
516 odata |= DUART_TX_READY;
517
518 vm_clear_irq(vm,C7200_DUART_IRQ);
519 *data = odata;
520 }
521 break;
522
523 case 0x414: /* Command Register A (CRA) */
524 /* Disable TX = High */
525 if ((op_type == MTS_WRITE) && (*data & 0x8)) {
526 vm->vtty_con->managed_flush = TRUE;
527 vtty_flush(vm->vtty_con);
528 }
529 break;
530
531 case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */
532 if (op_type == MTS_WRITE) {
533 vtty_put_char(vm->vtty_con,(char)*data);
534 d->duart_isr &= ~DUART_TXRDYA;
535 } else {
536 *data = vtty_get_char(vm->vtty_con);
537 d->duart_isr &= ~DUART_RXRDYA;
538 }
539 break;
540
541 case 0x424: /* WRITE: Aux Control Register (ACR) */
542 break;
543
544 case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */
545 if (op_type == MTS_WRITE) {
546 d->duart_imr = *data;
547 } else
548 *data = d->duart_isr;
549 break;
550
551 case 0x434: /* Counter/Timer Upper Value (CTU) */
552 case 0x43c: /* Counter/Timer Lower Value (CTL) */
553 case 0x444: /* Mode Register B (MRB) */
554 break;
555
556 case 0x44c: /* Status Register B (SRB) */
557 if (op_type == MTS_READ) {
558 odata = 0;
559
560 if (vtty_is_char_avail(vm->vtty_aux))
561 odata |= DUART_RX_READY;
562
563 odata |= DUART_TX_READY;
564
565 //vm_clear_irq(vm,C7200_DUART_IRQ);
566 *data = odata;
567 }
568 break;
569
570 case 0x454: /* Command Register B (CRB) */
571 /* Disable TX = High */
572 if ((op_type == MTS_WRITE) && (*data & 0x8)) {
573 vm->vtty_aux->managed_flush = TRUE;
574 vtty_flush(vm->vtty_aux);
575 }
576 break;
577
578 case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */
579 if (op_type == MTS_WRITE) {
580 vtty_put_char(vm->vtty_aux,(char)*data);
581 d->duart_isr &= ~DUART_TXRDYA;
582 } else {
583 *data = vtty_get_char(vm->vtty_aux);
584 d->duart_isr &= ~DUART_RXRDYB;
585 }
586 break;
587
588 case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */
589 case 0x474: /* READ: Start Counter Command; */
590 /* WRITE: Set Output Port Bits Command */
591 case 0x47c: /* WRITE: Reset Output Port Bits Command */
592 break;
593
594 /* ==== DS 1620 (temp sensors) ==== */
595 case 0x20c: /* Temperature Control */
596 if (op_type == MTS_WRITE)
597 temp_write_ctrl(d,*data);
598 break;
599
600 case 0x214: /* Temperature data write */
601 if (op_type == MTS_WRITE) {
602 temp_write_data(d,*data);
603 d->mux = *data;
604 }
605 break;
606
607 case 0x22c: /* Temperature data read */
608 if (op_type == MTS_READ)
609 *data = temp_read_data(d);
610 break;
611
612 /*
613 * NPE-G1 - Voltages + Power Supplies.
614 * I don't understand exactly how it works, it seems that the low
615 * part must be equal to the high part to have the better values.
616 */
617 case 0x254:
618 #if DEBUG_ENVM
619 vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
620 #endif
621 if (op_type == MTS_READ)
622 *data = 0xFFFFFFFF;
623 break;
624
625 case 0x257: /* ENVM A/D Converter */
626 #if DEBUG_ENVM
627 vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
628 #endif
629 if (op_type == MTS_READ) {
630 switch(d->mux) {
631 case C7200_MUX_PS0:
632 *data = C7200_A2D_PS0;
633 break;
634
635 case C7200_MUX_PS1:
636 *data = C7200_A2D_PS1;
637 break;
638
639 case C7200_MUX_P3V:
640 *data = C7200_A2D_P3V;
641 break;
642
643 case C7200_MUX_P12V:
644 *data = C7200_A2D_P12V;
645 break;
646
647 case C7200_MUX_P5V:
648 *data = C7200_A2D_P5V;
649 break;
650
651 case C7200_MUX_N12V:
652 *data = C7200_A2D_N12V;
653 break;
654
655 default:
656 *data = 0;
657 }
658
659 *data = *data / C7200_A2D_SAMPLES;
660 }
661 break;
662
663 /* NPE-G2 environmental monitor reading */
664 case 0x3c0:
665 if (op_type == MTS_READ)
666 *data = 0;
667 break;
668
669 case 0x3c4:
670 if (op_type == MTS_WRITE)
671 d->envm_r0 = ntohl(*data);
672 break;
673
674 case 0x3c8:
675 if (op_type == MTS_WRITE) {
676 d->envm_r1 = ntohl(*data);
677 } else {
678 *data = g2_envm_read(d);
679 }
680 break;
681
682 case 0x3cc:
683 if (op_type == MTS_WRITE)
684 d->envm_r2 = ntohl(*data);
685 break;
686
687 /* PCMCIA status ? */
688 case 0x3d6:
689 if (op_type == MTS_READ)
690 *data = 0x33;
691 break;
692
693 #if DEBUG_UNKNOWN
694 default:
695 if (op_type == MTS_READ) {
696 cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n",
697 offset,cpu_get_pc(cpu),op_size);
698 } else {
699 cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, "
700 "pc=0x%llx (size=%u)\n",
701 offset,*data,cpu_get_pc(cpu),op_size);
702 }
703 #endif
704 }
705
706 IOFPGA_UNLOCK(d);
707 return NULL;
708 }
709
710 /* Initialize EEPROM groups */
711 void c7200_init_eeprom_groups(c7200_t *router)
712 {
713 router->sys_eeprom_g1 = eeprom_cpu_midplane;
714 router->sys_eeprom_g2 = eeprom_pem_npeb;
715
716 router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom;
717 router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom;
718
719 router->sys_eeprom_g2.eeprom[0] = &router->pem_eeprom;
720 }
721
722 /* Shutdown the IO FPGA device */
723 void dev_c7200_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d)
724 {
725 if (d != NULL) {
726 IOFPGA_LOCK(d);
727 vm->vtty_con->read_notifier = NULL;
728 vm->vtty_aux->read_notifier = NULL;
729 IOFPGA_UNLOCK(d);
730
731 /* Remove the dummy IRQ periodic task */
732 ptask_remove(d->duart_irq_tid);
733
734 /* Remove the device */
735 dev_remove(vm,&d->dev);
736
737 /* Free the structure itself */
738 free(d);
739 }
740 }
741
742 /*
743 * dev_c7200_iofpga_init()
744 */
745 int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len)
746 {
747 vm_instance_t *vm = router->vm;
748 struct iofpga_data *d;
749 u_int i;
750
751 /* Allocate private data structure */
752 if (!(d = malloc(sizeof(*d)))) {
753 fprintf(stderr,"IO_FPGA: out of memory\n");
754 return(-1);
755 }
756
757 memset(d,0,sizeof(*d));
758
759 pthread_mutex_init(&d->lock,NULL);
760 d->router = router;
761
762 for(i=0;i<C7200_TEMP_SENSORS;i++) {
763 d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU;
764 d->temp_deg_reg[i] = C7200_DEFAULT_TEMP * 2;
765 }
766
767 vm_object_init(&d->vm_obj);
768 d->vm_obj.name = "io_fpga";
769 d->vm_obj.data = d;
770 d->vm_obj.shutdown = (vm_shutdown_t)dev_c7200_iofpga_shutdown;
771
772 /* Set device properties */
773 dev_init(&d->dev);
774 d->dev.name = "io_fpga";
775 d->dev.phys_addr = paddr;
776 d->dev.phys_len = len;
777 d->dev.handler = dev_c7200_iofpga_access;
778 d->dev.priv_data = d;
779
780 /* If we have an I/O slot, we use the I/O slot DUART */
781 if (c7200_pa_check_eeprom(d->router,0)) {
782 vm_log(vm,"CONSOLE","console managed by I/O board\n");
783
784 /* Set console and AUX port notifying functions */
785 vm->vtty_con->priv_data = d;
786 vm->vtty_aux->priv_data = d;
787 vm->vtty_con->read_notifier = tty_con_input;
788 vm->vtty_aux->read_notifier = tty_aux_input;
789
790 /* Trigger periodically a dummy IRQ to flush buffers */
791 d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,
792 d,NULL);
793 }
794
795 /* Map this device to the VM */
796 vm_bind_device(vm,&d->dev);
797 vm_object_add(vm,&d->vm_obj);
798 return(0);
799 }

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