/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_c3600_iofpga.c
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Annotation of /upstream/dynamips-0.2.7-RC2/dev_c3600_iofpga.c

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Revision 8 - (hide annotations)
Sat Oct 6 16:24:54 2007 UTC (13 years ago) by dpavlin
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File size: 20357 byte(s)
dynamips-0.2.7-RC2

1 dpavlin 1 /*
2 dpavlin 8 * Cisco router simulation platform.
3 dpavlin 1 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4     *
5     * TODO: Online Insertion/Removal (OIR).
6     */
7    
8     #include <stdio.h>
9     #include <stdlib.h>
10     #include <string.h>
11     #include <unistd.h>
12     #include <sys/types.h>
13     #include <termios.h>
14     #include <fcntl.h>
15     #include <pthread.h>
16    
17     #include "ptask.h"
18 dpavlin 7 #include "cpu.h"
19     #include "vm.h"
20 dpavlin 1 #include "dynamips.h"
21     #include "memory.h"
22     #include "device.h"
23     #include "dev_vtty.h"
24 dpavlin 8 #include "nmc93cX6.h"
25 dpavlin 1 #include "dev_c3600.h"
26    
27     /* Debugging flags */
28     #define DEBUG_UNKNOWN 1
29     #define DEBUG_ACCESS 0
30 dpavlin 8 #define DEBUG_NET_IRQ 0
31 dpavlin 1
32     /* Definitions for Mainboard EEPROM */
33     #define EEPROM_MB_DOUT 3
34     #define EEPROM_MB_DIN 2
35     #define EEPROM_MB_CLK 1
36     #define EEPROM_MB_CS 0
37    
38     /* Definitions for Network Modules EEPROM */
39     #define EEPROM_NM_DOUT 7
40     #define EEPROM_NM_DIN 6
41     #define EEPROM_NM_CLK 2
42     #define EEPROM_NM_CS 4
43    
44 dpavlin 8 /* Network IRQ distribution */
45     struct net_irq_distrib {
46     u_int c3620_c3640_offset;
47     u_int c3660_reg;
48     u_int c3660_offset;
49     };
50 dpavlin 2
51 dpavlin 8 /*
52     * Network IRQ distribution for c3620/c3640
53     *
54     * Slot 0 | 3620/3640: reg 0x20001 | 3660: reg 0x20010, offset 0
55     * Slot 1 | 3620/3640: reg 0x20000 | 3660: reg 0x10010, offset 24
56     * Slot 2 | 3640 : reg 0x20003 | 3660: reg 0x10010, offset 16
57     * Slot 3 | 3640 : reg 0x20002 | 3660: reg 0x10010, offset 28
58     * Slot 4 | 3620/3640: N/A | 3660: reg 0x10010, offset 20
59     * Slot 5 | 3620/3640: N/A | 3660: reg 0x10010, offset 8
60     * Slot 6 | 3620/3640: N/A | 3660: reg 0x10010, offset 0
61     */
62     static struct net_irq_distrib net_irq_dist[C3600_MAX_NM_BAYS] = {
63     { 16, 1, 0 },
64     { 24, 0, 24 },
65     { 0, 0, 16 },
66     { 8, 0, 28 },
67     { 32, 0, 20 },
68     { 32, 0, 8 },
69     { 32, 0, 0 },
70     };
71    
72 dpavlin 1 /* IO FPGA structure */
73 dpavlin 8 struct c3600_iofpga_data {
74 dpavlin 1 vm_obj_t vm_obj;
75     struct vdevice dev;
76     c3600_t *router;
77 dpavlin 2
78 dpavlin 8 /* Network IRQ status */
79     m_uint32_t net_irq_status[2];
80    
81 dpavlin 1 /* Slot select for EEPROM access */
82     u_int eeprom_slot;
83    
84     /* IO Mask. Don't know the meaning */
85     m_uint8_t io_mask;
86    
87     m_uint16_t sel;
88     };
89    
90     /* Mainboard EEPROM definition */
91 dpavlin 8 static const struct nmc93cX6_eeprom_def eeprom_mb_def = {
92 dpavlin 1 EEPROM_MB_CLK, EEPROM_MB_CS,
93     EEPROM_MB_DIN, EEPROM_MB_DOUT,
94     };
95    
96     /* Mainboard EEPROM */
97 dpavlin 8 static const struct nmc93cX6_group eeprom_mb_group = {
98     EEPROM_TYPE_NMC93C46, 1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def },
99 dpavlin 1 };
100    
101     /* NM EEPROM definition */
102 dpavlin 8 static const struct nmc93cX6_eeprom_def eeprom_nm_def = {
103 dpavlin 1 EEPROM_NM_CLK, EEPROM_NM_CS,
104     EEPROM_NM_DIN, EEPROM_NM_DOUT,
105     };
106    
107     /* NM EEPROM */
108 dpavlin 8 static const struct nmc93cX6_group eeprom_nm_group = {
109     EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def },
110 dpavlin 1 };
111    
112     /* C3660 NM presence masks */
113     static const m_uint16_t c3660_nm_masks[6] = {
114     0xF0FF, /* slot 1 */
115     0xFFF0, /* slot 2 */
116     0x0FFF, /* slot 3 */
117     0xFF0F, /* slot 4 */
118     0xF0FF, /* slot 5 */
119     0xFFF0, /* slot 6 */
120     };
121    
122     /* Select the current NM EEPROM */
123 dpavlin 8 static void nm_eeprom_select(struct c3600_iofpga_data *d,u_int slot)
124 dpavlin 1 {
125 dpavlin 3 d->router->nm_eeprom_group.eeprom[0] = &d->router->nm_bay[slot].eeprom;
126 dpavlin 1 }
127    
128     /* Return the NM status register given the detected EEPROM (3620/3640) */
129 dpavlin 8 static u_int nm_get_status_1(struct c3600_iofpga_data *d)
130 dpavlin 1 {
131     u_int res = 0xFFFF;
132     int i;
133    
134     for(i=0;i<4;i++) {
135     if (c3600_nm_check_eeprom(d->router,i))
136     res &= ~(0x1111 << i);
137     }
138    
139     return(res);
140     }
141    
142     /* Return the NM status register given the detected EEPROM (3660) */
143 dpavlin 8 static u_int nm_get_status_2(struct c3600_iofpga_data *d,u_int pos)
144 dpavlin 1 {
145     u_int res = 0xFFFF;
146     u_int start,end;
147     int i;
148    
149     switch(pos) {
150     case 0: /* word 0: slot 1 - 4 */
151     start = 1;
152     end = 4;
153     break;
154     case 1: /* word 1: slot 5 - 6 */
155     start = 5;
156     end = 6;
157     break;
158     default:
159     return(res);
160     }
161    
162     for(i=start;i<=end;i++) {
163     if (c3600_nm_check_eeprom(d->router,i))
164     res &= c3660_nm_masks[i-1];
165     }
166    
167     return(res);
168     }
169    
170 dpavlin 8 /* Update network interrupt status */
171     static inline void
172     dev_c3620_c3640_iofpga_net_update_irq(struct c3600_iofpga_data *d)
173     {
174     if (d->net_irq_status[0]) {
175     vm_set_irq(d->router->vm,C3600_NETIO_IRQ);
176     } else {
177     vm_clear_irq(d->router->vm,C3600_NETIO_IRQ);
178     }
179     }
180    
181     static inline void
182     dev_c3660_iofpga_net_update_irq(struct c3600_iofpga_data *d)
183     {
184     if (d->net_irq_status[0] || d->net_irq_status[1]) {
185     vm_set_irq(d->router->vm,C3600_NETIO_IRQ);
186     } else {
187     vm_clear_irq(d->router->vm,C3600_NETIO_IRQ);
188     }
189     }
190    
191     /* Trigger a Network IRQ for the specified slot/port */
192     void dev_c3600_iofpga_net_set_irq(struct c3600_iofpga_data *d,
193     u_int slot,u_int port)
194     {
195     struct net_irq_distrib *irq_dist;
196    
197     #if DEBUG_NET_IRQ
198     vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n",
199     slot,port);
200     #endif
201    
202     irq_dist = &net_irq_dist[slot];
203    
204     switch(c3600_chassis_get_id(d->router)) {
205     case 3620:
206     case 3640:
207     d->net_irq_status[0] |= (1 << (irq_dist->c3620_c3640_offset + port));
208     dev_c3620_c3640_iofpga_net_update_irq(d);
209     break;
210     case 3660:
211     d->net_irq_status[irq_dist->c3660_reg] |=
212     (1 << (irq_dist->c3660_offset + port));
213     dev_c3660_iofpga_net_update_irq(d);
214     break;
215     }
216     }
217    
218     /* Clear a Network IRQ for the specified slot/port */
219     void dev_c3600_iofpga_net_clear_irq(struct c3600_iofpga_data *d,
220     u_int slot,u_int port)
221     {
222     struct net_irq_distrib *irq_dist;
223    
224     #if DEBUG_NET_IRQ
225     vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n",
226     slot,port);
227     #endif
228    
229     irq_dist = &net_irq_dist[slot];
230    
231     switch(c3600_chassis_get_id(d->router)) {
232     case 3620:
233     case 3640:
234     d->net_irq_status[0] &= ~(1 << (irq_dist->c3620_c3640_offset + port));
235     dev_c3620_c3640_iofpga_net_update_irq(d);
236     break;
237     case 3660:
238     d->net_irq_status[irq_dist->c3660_reg] &=
239     ~(1 << (irq_dist->c3660_offset + port));
240     dev_c3660_iofpga_net_update_irq(d);
241     break;
242     }
243     }
244    
245 dpavlin 1 /*
246     * dev_c3620_c3640_iofpga_access()
247     */
248     static void *
249 dpavlin 7 dev_c3620_c3640_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
250 dpavlin 1 m_uint32_t offset,u_int op_size,u_int op_type,
251     m_uint64_t *data)
252     {
253 dpavlin 8 struct c3600_iofpga_data *d = dev->priv_data;
254 dpavlin 1
255     if (op_type == MTS_READ)
256     *data = 0x0;
257    
258     #if DEBUG_ACCESS
259     if (offset != 0x0c) {
260     if (op_type == MTS_READ) {
261     cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
262 dpavlin 7 offset,cpu_get_pc(cpu),op_size);
263 dpavlin 1 } else {
264     cpu_log(cpu,"IO_FPGA",
265     "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
266 dpavlin 7 offset,cpu_get_pc(cpu),*data,op_size);
267 dpavlin 1 }
268     }
269     #endif
270    
271     switch(offset) {
272     /* Probably flash protection (if 0, no write access allowed) */
273     case 0x00008:
274     if (op_type == MTS_READ)
275     *data = 0xFF;
276     break;
277    
278     /* Bootflash of 8 Mb */
279     case 0x0000a:
280     if (op_type == MTS_READ)
281     *data = 0x1000;
282     break;
283    
284     /*
285     * 0x7d00 is written here regularly.
286     * Some kind of hardware watchdog ?
287     */
288     case 0x0000c:
289     break;
290    
291     /* Mainboard EEPROM */
292     case 0x0000e:
293     if (op_type == MTS_WRITE)
294 dpavlin 8 nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
295 dpavlin 1 else
296 dpavlin 8 *data = nmc93cX6_read(&d->router->mb_eeprom_group);
297 dpavlin 1 break;
298    
299     case 0x10004: /* ??? OIR control ??? */
300     if (op_type == MTS_READ) {
301     *data = 0x0000;
302     }
303     break;
304    
305     /*
306     * Network modules presence.
307     *
308     * Bit 0: 0 = NM in slot 0 is valid
309     * Bit 1: 0 = NM in slot 1 is valid
310     * Bit 2: 0 = NM in slot 2 is valid
311     * Bit 3: 0 = NM in slot 3 is valid
312     *
313     * Very well explained on Cisco website:
314     * http://www.cisco.com/en/US/customer/products/hw/routers/ps274/products_tech_note09186a0080109510.shtml
315     */
316     case 0x10006:
317     if (op_type == MTS_READ)
318     *data = nm_get_status_1(d);
319     break;
320    
321     /*
322     * NM EEPROMs.
323     */
324     case 0x10008:
325     if (op_type == MTS_WRITE) {
326     d->eeprom_slot = *data & 0x03;
327     nm_eeprom_select(d,d->eeprom_slot);
328 dpavlin 8 nmc93cX6_write(&d->router->nm_eeprom_group,*data);
329 dpavlin 1 } else {
330 dpavlin 8 *data = nmc93cX6_read(&d->router->nm_eeprom_group);
331 dpavlin 1 }
332     break;
333    
334     /* Network interrupt status */
335 dpavlin 8 case 0x20000: /* slot 1 */
336 dpavlin 1 if (op_type == MTS_READ)
337 dpavlin 8 *data = d->net_irq_status[0] >> 24;
338 dpavlin 1 break;
339 dpavlin 8 case 0x20001: /* slot 0 */
340     if (op_type == MTS_READ)
341     *data = d->net_irq_status[0] >> 16;
342     break;
343     case 0x20002: /* slot 3 */
344     if (op_type == MTS_READ)
345     *data = d->net_irq_status[0] >> 8;
346     break;
347     case 0x20003: /* slot 2 */
348     if (op_type == MTS_READ)
349     *data = d->net_irq_status[0];
350     break;
351 dpavlin 1
352     /*
353     * Read when a PA Management interrupt is triggered.
354     *
355     * If not 0, we get:
356     * "Error: Unexpected NM Interrupt received from slot: x"
357     */
358     case 0x20004:
359     if (op_type == MTS_READ)
360     *data = 0x00;
361     vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
362     break;
363    
364     /*
365     * Read when an external interrupt is triggered.
366     *
367     * Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
368     * Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
369     *
370     * oir_ctrl = register 0x10004
371     * oir_stat = register 0x10006
372     */
373     case 0x20006:
374     if (op_type == MTS_READ)
375     *data = 0x00;
376     vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
377     break;
378    
379     /* IO Mask (displayed by "show c3600") */
380     case 0x20008:
381     if (op_type == MTS_READ)
382     *data = d->io_mask;
383     else
384     d->io_mask = *data;
385     break;
386    
387 dpavlin 5 /*
388     * Platform type ?
389     * 0: 3640, 4 << 5: 3620, 3 << 5: 3660
390     */
391 dpavlin 1 case 0x30000:
392     if (op_type == MTS_READ) {
393     switch(c3600_chassis_get_id(d->router)) {
394     case 3620:
395     *data = 4 << 5;
396     break;
397     case 3640:
398     *data = 0 << 5;
399     break;
400     case 3660:
401     *data = 3 << 5;
402     break;
403     default:
404     *data = 0;
405     }
406     }
407     break;
408    
409     /* ??? */
410     case 0x30002:
411     if (op_type == MTS_WRITE) {
412     d->sel = *data;
413     } else {
414     //*data = d->sel;
415     }
416     break;
417    
418     /*
419     * Environmental parameters, determined with "sh env all".
420     *
421     * Bit 0: 0 = overtemperature condition.
422     * Bit 4: 0 = RPS present.
423     * Bit 5: 0 = Input Voltage status failure.
424     * Bit 6: 1 = Thermal status failure.
425     * Bit 7: 1 = DC Output Voltage status failure.
426     */
427     case 0x30004:
428     if (op_type == MTS_READ) {
429     *data = 32 + 1;
430     }
431     break;
432    
433     #if DEBUG_UNKNOWN
434     default:
435     if (op_type == MTS_READ) {
436     cpu_log(cpu,"IO_FPGA",
437     "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
438 dpavlin 7 offset,cpu_get_pc(cpu),op_size);
439 dpavlin 1 } else {
440     cpu_log(cpu,"IO_FPGA",
441     "write to unknown addr 0x%x, value=0x%llx, "
442 dpavlin 7 "pc=0x%llx (size=%u)\n",
443     offset,*data,cpu_get_pc(cpu),op_size);
444 dpavlin 1 }
445     #endif
446     }
447    
448     return NULL;
449     }
450    
451     /*
452     * dev_c3660_iofpga_access()
453     */
454     static void *
455 dpavlin 7 dev_c3660_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
456 dpavlin 1 m_uint32_t offset,u_int op_size,u_int op_type,
457     m_uint64_t *data)
458     {
459 dpavlin 8 struct c3600_iofpga_data *d = dev->priv_data;
460 dpavlin 1 u_int slot;
461    
462     if (op_type == MTS_READ)
463     *data = 0x0;
464    
465     #if DEBUG_ACCESS
466     if (offset != 0x0c) {
467     if (op_type == MTS_READ) {
468     cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
469 dpavlin 7 offset,cpu_get_pc(cpu),op_size);
470 dpavlin 1 } else {
471     cpu_log(cpu,"IO_FPGA",
472     "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
473 dpavlin 7 offset,cpu_get_pc(cpu),*data,op_size);
474 dpavlin 1 }
475     }
476     #endif
477    
478     switch(offset) {
479     /*
480     * 0x7d00 is written here regularly.
481     * Some kind of hardware watchdog ?
482     */
483     case 0x0000c:
484     break;
485    
486     /* Probably flash protection (if 0, no write access allowed) */
487     case 0x00008:
488     if (op_type == MTS_READ)
489     *data = 0xFF;
490     break;
491    
492     /* Bootflash of 8 Mb */
493     case 0x0000a:
494     if (op_type == MTS_READ)
495     *data = 0x1000;
496     break;
497    
498     /* NM presence - slots 1 to 4 */
499     case 0x10006:
500     if (op_type == MTS_READ)
501     *data = nm_get_status_2(d,0);
502     break;
503    
504     /* NM presence - slot 5 to 6 */
505     case 0x10008:
506     if (op_type == MTS_READ)
507     *data = nm_get_status_2(d,1);
508     break;
509    
510     /* Fan status, PS presence */
511     case 0x10018:
512     if (op_type == MTS_READ)
513     *data = 0x0000;
514     break;
515    
516     /* unknown, read by env monitor */
517     case 0x1001a:
518     if (op_type == MTS_READ)
519     *data = 0x0000;
520     break;
521    
522     /* board temperature */
523     case 0x30004:
524     if (op_type == MTS_READ) {
525     *data = 32 + 1;
526     }
527     break;
528    
529     /* sh c3600: Per Slot Intr Mask */
530     case 0x10016:
531     if (op_type == MTS_READ)
532     *data = 0x12;
533     break;
534    
535     /* sh c3600: OIR fsm state slot's (12) */
536     case 0x10020:
537     if (op_type == MTS_READ)
538     *data = 0x00;
539     break;
540    
541     /* sh c3600: OIR fsm state slot's (34) */
542     case 0x10022:
543     if (op_type == MTS_READ)
544     *data = 0x00;
545     break;
546    
547     /* sh c3600: OIR fsm state slot's (56) */
548     case 0x10024:
549     if (op_type == MTS_READ)
550     *data = 0x00;
551     break;
552    
553     /*
554     * Backplane EEPROM.
555     *
556     * Bit 7: 0=Telco chassis, 1=Enterprise chassis.
557     */
558     case 0x10000:
559     if (op_type == MTS_WRITE)
560 dpavlin 8 nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
561 dpavlin 1 else
562 dpavlin 8 *data = nmc93cX6_read(&d->router->mb_eeprom_group) | 0x80;
563 dpavlin 1 break;
564    
565     /* NM EEPROMs - slots 1 to 6 */
566     case 0x1000a:
567     case 0x1000b:
568     case 0x1000c:
569     case 0x1000d:
570     case 0x1000e:
571     case 0x1000f:
572     slot = (offset - 0x1000a) + 1;
573    
574     if (op_type == MTS_WRITE) {
575 dpavlin 8 nmc93cX6_write(&d->router->c3660_nm_eeprom_group[slot],
576 dpavlin 1 (u_int)(*data));
577     } else {
578 dpavlin 8 *data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[slot]);
579 dpavlin 1 }
580     break;
581    
582     /* NM EEPROM - slot 0 */
583     case 0x20006:
584     if (op_type == MTS_WRITE) {
585 dpavlin 8 nmc93cX6_write(&d->router->c3660_nm_eeprom_group[0],
586 dpavlin 1 (u_int)(*data));
587     } else {
588 dpavlin 8 *data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[0]);
589 dpavlin 1 }
590     break;
591    
592     /* Unknown EEPROMs ? */
593     case 0x20000:
594     case 0x20002:
595     case 0x20004:
596     if (op_type == MTS_READ)
597     *data = 0xFFFF;
598     break;
599    
600     /* IO Mask (displayed by "show c3600") */
601     case 0x20008:
602     if (op_type == MTS_READ)
603     *data = d->io_mask;
604     else
605     d->io_mask = *data;
606     break;
607    
608     /* 0: 3640, 4 << 5: 3620, 3 << 5: 3660 */
609     case 0x30000:
610     if (op_type == MTS_READ)
611     *data = 3 << 5;
612     break;
613    
614     /* ??? */
615     case 0x30008:
616     if (op_type == MTS_READ)
617     *data = 0xFF;
618     break;
619    
620     /*
621     * Read at net interrupt (size 4).
622     * It seems that there are 4 lines per slot.
623     *
624     * Bit 24-27: slot 1
625     * Bit 16-19: slot 2
626     * Bit 28-31: slot 3
627     * Bit 20-23: slot 4
628     * Bit 08-11: slot 5
629     * Bit 00-03: slot 6
630     *
631     * Other bits are unknown.
632     */
633     case 0x10010:
634     if (op_type == MTS_READ)
635 dpavlin 8 *data = d->net_irq_status[0];
636 dpavlin 1 break;
637    
638     /*
639     * Read at net interrupt (size 1)
640     *
641     * Bit 7-6: we get "Unexpected AIM interrupt on AIM slot 1".
642     * Bit 5-4: we get "Unexpected AIM interrupt on AIM slot 0".
643     * Bit 0-3: net interrupt for slot 0.
644     */
645     case 0x20010:
646     if (op_type == MTS_READ)
647 dpavlin 8 *data = d->net_irq_status[1];
648 dpavlin 1 break;
649    
650     /*
651     * Read when a PA Management interrupt is triggered.
652     *
653     * If not 0, we get:
654     * "Error: Unexpected NM Interrupt received from slot: x"
655     */
656     case 0x10014:
657     if (op_type == MTS_READ)
658     *data = 0x00;
659     vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
660     break;
661    
662     /*
663     * Read when an external interrupt is triggered.
664     *
665     * Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
666     * Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
667     *
668     * oir_ctrl = register 0x10004
669     * oir_stat = register 0x10006
670     */
671     case 0x2000a:
672     if (op_type == MTS_READ)
673     *data = 0x54;
674     vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
675     break;
676    
677     #if DEBUG_UNKNOWN
678     default:
679     if (op_type == MTS_READ) {
680     cpu_log(cpu,"IO_FPGA",
681     "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
682 dpavlin 7 offset,cpu_get_pc(cpu),op_size);
683 dpavlin 1 } else {
684     cpu_log(cpu,"IO_FPGA",
685     "write to unknown addr 0x%x, value=0x%llx, "
686 dpavlin 7 "pc=0x%llx (size=%u)\n",
687     offset,*data,cpu_get_pc(cpu),op_size);
688 dpavlin 1 }
689     #endif
690     }
691    
692     return NULL;
693     }
694    
695     /* Initialize EEPROM groups */
696     void c3600_init_eeprom_groups(c3600_t *router)
697     {
698     int i;
699    
700 dpavlin 3 /* Initialize Mainboard EEPROM */
701     router->mb_eeprom_group = eeprom_mb_group;
702     router->mb_eeprom_group.eeprom[0] = &router->mb_eeprom;
703     router->mb_eeprom.data = NULL;
704     router->mb_eeprom.len = 0;
705 dpavlin 1
706 dpavlin 3 /* Initialize NM EEPROM for 3620/3640 */
707     router->nm_eeprom_group = eeprom_nm_group;
708     router->nm_eeprom_group.eeprom[0] = NULL;
709 dpavlin 1
710 dpavlin 3 /* Initialize NM EEPROM for 3660 */
711 dpavlin 1 for(i=0;i<C3600_MAX_NM_BAYS;i++) {
712 dpavlin 3 router->c3660_nm_eeprom_group[i] = eeprom_nm_group;
713     router->c3660_nm_eeprom_group[i].eeprom[0] = &router->nm_bay[i].eeprom;
714 dpavlin 1 }
715     }
716    
717     /* Shutdown the IO FPGA device */
718 dpavlin 8 static void
719     dev_c3600_iofpga_shutdown(vm_instance_t *vm,struct c3600_iofpga_data *d)
720 dpavlin 1 {
721     if (d != NULL) {
722     /* Remove the device */
723     dev_remove(vm,&d->dev);
724    
725     /* Free the structure itself */
726     free(d);
727     }
728     }
729    
730     /*
731     * dev_c3600_iofpga_init()
732     */
733     int dev_c3600_iofpga_init(c3600_t *router,m_uint64_t paddr,m_uint32_t len)
734     {
735     vm_instance_t *vm = router->vm;
736 dpavlin 8 struct c3600_iofpga_data *d;
737 dpavlin 1
738     /* Allocate private data structure */
739     if (!(d = malloc(sizeof(*d)))) {
740     fprintf(stderr,"IO_FPGA: out of memory\n");
741     return(-1);
742     }
743    
744     memset(d,0,sizeof(*d));
745     d->router = router;
746    
747     vm_object_init(&d->vm_obj);
748     d->vm_obj.name = "io_fpga";
749     d->vm_obj.data = d;
750     d->vm_obj.shutdown = (vm_shutdown_t)dev_c3600_iofpga_shutdown;
751    
752     /* Set device properties */
753     dev_init(&d->dev);
754     d->dev.name = "io_fpga";
755     d->dev.phys_addr = paddr;
756     d->dev.phys_len = len;
757     d->dev.priv_data = d;
758    
759     switch(router->chassis_driver->chassis_id) {
760     case 3620:
761     case 3640:
762     d->dev.handler = dev_c3620_c3640_iofpga_access;
763     break;
764     case 3660:
765     d->dev.handler = dev_c3660_iofpga_access;
766     break;
767     default:
768     fprintf(stderr,"C3600 '%s': invalid chassis ID %d\n",
769     router->vm->name,router->chassis_driver->chassis_id);
770     free(d);
771     return(-1);
772     }
773    
774     /* Map this device to the VM */
775     vm_bind_device(router->vm,&d->dev);
776     vm_object_add(vm,&d->vm_obj);
777     return(0);
778     }

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