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#include <pthread.h> |
#include <pthread.h> |
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|
|
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#include "ptask.h" |
#include "ptask.h" |
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#include "mips64.h" |
#include "cpu.h" |
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|
#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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* dev_c3620_c3640_iofpga_access() |
* dev_c3620_c3640_iofpga_access() |
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*/ |
*/ |
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static void * |
static void * |
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dev_c3620_c3640_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
dev_c3620_c3640_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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if (offset != 0x0c) { |
if (offset != 0x0c) { |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
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} |
} |
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} |
} |
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#endif |
#endif |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
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|
offset,*data,cpu_get_pc(cpu),op_size); |
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} |
} |
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#endif |
#endif |
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} |
} |
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* dev_c3660_iofpga_access() |
* dev_c3660_iofpga_access() |
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*/ |
*/ |
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static void * |
static void * |
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dev_c3660_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
dev_c3660_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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if (offset != 0x0c) { |
if (offset != 0x0c) { |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
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} |
} |
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} |
} |
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#endif |
#endif |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
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|
offset,*data,cpu_get_pc(cpu),op_size); |
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} |
} |
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#endif |
#endif |
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} |
} |