/[dynamips]/upstream/dynamips-0.2.7-RC2/cpu.h
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Contents of /upstream/dynamips-0.2.7-RC2/cpu.h

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Revision 8 - (show annotations)
Sat Oct 6 16:24:54 2007 UTC (12 years, 1 month ago) by dpavlin
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dynamips-0.2.7-RC2

1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4 */
5
6 #ifndef __CPU_H__
7 #define __CPU_H__
8
9 #include <pthread.h>
10 #include "utils.h"
11
12 /* Forward declaration for generic CPU type */
13 typedef struct cpu_gen cpu_gen_t;
14
15 #include "mips64.h"
16 #include "mips64_cp0.h"
17 #include "ppc32.h"
18
19 /* Possible CPU types */
20 enum {
21 CPU_TYPE_MIPS64 = 1,
22 CPU_TYPE_PPC32,
23 };
24
25 /* Virtual CPU states */
26 enum {
27 CPU_STATE_RUNNING = 0,
28 CPU_STATE_HALTED,
29 CPU_STATE_SUSPENDED,
30 };
31
32 /* Maximum results for idle pc */
33 #define CPU_IDLE_PC_MAX_RES 10
34
35 /* Idle PC proposed value */
36 struct cpu_idle_pc {
37 m_uint64_t pc;
38 u_int count;
39 };
40
41 /* Number of recorded memory accesses (power of two) */
42 #define MEMLOG_COUNT 16
43
44 typedef struct memlog_access memlog_access_t;
45 struct memlog_access {
46 m_uint64_t iaddr;
47 m_uint64_t vaddr;
48 m_uint64_t data;
49 m_uint32_t data_valid;
50 m_uint32_t op_size;
51 m_uint32_t op_type;
52 };
53
54 /* Generic CPU definition */
55 struct cpu_gen {
56 /* CPU type and identifier for MP systems */
57 u_int type,id;
58
59 /* CPU states */
60 volatile u_int state,prev_state;
61 volatile m_uint64_t seq_state;
62
63 /* Thread running this CPU */
64 pthread_t cpu_thread;
65 int cpu_thread_running;
66
67 /* "Idle" loop management */
68 u_int idle_count,idle_max,idle_sleep_time;
69 pthread_mutex_t idle_mutex;
70 pthread_cond_t idle_cond;
71
72 /* VM instance */
73 vm_instance_t *vm;
74
75 /* Next CPU in group */
76 cpu_gen_t *next;
77
78 /* Idle PC proposal */
79 struct cpu_idle_pc idle_pc_prop[CPU_IDLE_PC_MAX_RES];
80 u_int idle_pc_prop_count;
81
82 /* Specific CPU part */
83 union {
84 cpu_mips_t mips64_cpu;
85 cpu_ppc_t ppc32_cpu;
86 }sp;
87
88 /* Methods */
89 void (*reg_set)(cpu_gen_t *cpu,u_int reg_index,m_uint64_t val);
90 void (*reg_dump)(cpu_gen_t *cpu);
91 void (*mmu_dump)(cpu_gen_t *cpu);
92 void (*mmu_raw_dump)(cpu_gen_t *cpu);
93 void (*add_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr);
94 void (*remove_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr);
95 void (*set_idle_pc)(cpu_gen_t *cpu,m_uint64_t addr);
96 void (*get_idling_pc)(cpu_gen_t *cpu);
97 void (*mts_rebuild)(cpu_gen_t *cpu);
98 void (*mts_show_stats)(cpu_gen_t *cpu);
99
100 /* Memory access log for fault debugging */
101 u_int memlog_pos;
102 memlog_access_t memlog_array[MEMLOG_COUNT];
103
104 /* Statistics */
105 m_uint64_t dev_access_counter;
106 };
107
108 /* CPU group definition */
109 typedef struct cpu_group cpu_group_t;
110 struct cpu_group {
111 char *name;
112 cpu_gen_t *cpu_list;
113 void *priv_data;
114 };
115
116 #define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu)
117 #define CPU_PPC32(cpu) (&(cpu)->sp.ppc32_cpu)
118
119 /* Get CPU instruction pointer */
120 static forced_inline m_uint64_t cpu_get_pc(cpu_gen_t *cpu)
121 {
122 switch(cpu->type) {
123 case CPU_TYPE_MIPS64:
124 return(CPU_MIPS64(cpu)->pc);
125 case CPU_TYPE_PPC32:
126 return((m_uint64_t)CPU_PPC32(cpu)->ia);
127 default:
128 return(0);
129 }
130 }
131
132 /* Get CPU performance counter */
133 static forced_inline m_uint64_t cpu_get_perf_counter(cpu_gen_t *cpu)
134 {
135 switch(cpu->type) {
136 case CPU_TYPE_MIPS64:
137 return(CPU_MIPS64(cpu)->perf_counter);
138 case CPU_TYPE_PPC32:
139 return(CPU_PPC32(cpu)->perf_counter);
140 default:
141 return(0);
142 }
143 }
144
145 /* Find a CPU in a group given its ID */
146 cpu_gen_t *cpu_group_find_id(cpu_group_t *group,u_int id);
147
148 /* Find the highest CPU ID in a CPU group */
149 int cpu_group_find_highest_id(cpu_group_t *group,u_int *highest_id);
150
151 /* Add a CPU in a CPU group */
152 int cpu_group_add(cpu_group_t *group,cpu_gen_t *cpu);
153
154 /* Create a new CPU group */
155 cpu_group_t *cpu_group_create(char *name);
156
157 /* Delete a CPU group */
158 void cpu_group_delete(cpu_group_t *group);
159
160 /* Rebuild the MTS subsystem for a CPU group */
161 int cpu_group_rebuild_mts(cpu_group_t *group);
162
163 /* Log a message for a CPU */
164 void cpu_log(cpu_gen_t *cpu,char *module,char *format,...);
165
166 /* Create a new CPU */
167 cpu_gen_t *cpu_create(vm_instance_t *vm,u_int type,u_int id);
168
169 /* Delete a CPU */
170 void cpu_delete(cpu_gen_t *cpu);
171
172 /* Start a CPU */
173 void cpu_start(cpu_gen_t *cpu);
174
175 /* Stop a CPU */
176 void cpu_stop(cpu_gen_t *cpu);
177
178 /* Start all CPUs of a CPU group */
179 void cpu_group_start_all_cpu(cpu_group_t *group);
180
181 /* Stop all CPUs of a CPU group */
182 void cpu_group_stop_all_cpu(cpu_group_t *group);
183
184 /* Set a state of all CPUs of a CPU group */
185 void cpu_group_set_state(cpu_group_t *group,u_int state);
186
187 /* Synchronize on CPUs (all CPUs must be inactive) */
188 int cpu_group_sync_state(cpu_group_t *group);
189
190 /* Save state of all CPUs */
191 int cpu_group_save_state(cpu_group_t *group);
192
193 /* Restore state of all CPUs */
194 int cpu_group_restore_state(cpu_group_t *group);
195
196 /* Virtual idle loop */
197 void cpu_idle_loop(cpu_gen_t *cpu);
198
199 /* Break idle wait state */
200 void cpu_idle_break_wait(cpu_gen_t *cpu);
201
202 #endif

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