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dpavlin |
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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#ifndef __PPC_32_H__ |
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#define __PPC_32_H__ |
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#include <pthread.h> |
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#include "utils.h" |
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#include "rbtree.h" |
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/* CPU identifiers */ |
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#define PPC32_PVR_405 0x40110000 |
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/* Number of GPR (general purpose registers) */ |
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#define PPC32_GPR_NR 32 |
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/* Number of registers in FPU */ |
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#define PPC32_FPU_REG_NR 32 |
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/* Minimum page size: 4 Kb */ |
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#define PPC32_MIN_PAGE_SHIFT 12 |
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#define PPC32_MIN_PAGE_SIZE (1 << PPC32_MIN_PAGE_SHIFT) |
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#define PPC32_MIN_PAGE_IMASK (PPC32_MIN_PAGE_SIZE - 1) |
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#define PPC32_MIN_PAGE_MASK 0xFFFFF000 |
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/* Starting point for ROM */ |
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#define PPC32_ROM_START 0xfff00100 |
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#define PPC32_ROM_SP 0x00006000 |
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/* Special Purpose Registers (SPR) */ |
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#define PPC32_SPR_XER 1 |
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#define PPC32_SPR_LR 8 /* Link Register */ |
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#define PPC32_SPR_CTR 9 /* Count Register */ |
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#define PPC32_SPR_DSISR 18 |
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#define PPC32_SPR_DAR 19 |
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#define PPC32_SPR_DEC 22 /* Decrementer */ |
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#define PPC32_SPR_SDR1 25 /* Page Table Address */ |
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#define PPC32_SPR_SRR0 26 |
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#define PPC32_SPR_SRR1 27 |
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#define PPC32_SPR_TBL_READ 268 /* Time Base Low (read) */ |
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#define PPC32_SPR_TBU_READ 269 /* Time Base Up (read) */ |
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#define PPC32_SPR_SPRG0 272 |
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#define PPC32_SPR_SPRG1 273 |
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#define PPC32_SPR_SPRG2 274 |
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#define PPC32_SPR_SPRG3 275 |
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#define PPC32_SPR_TBL_WRITE 284 /* Time Base Low (write) */ |
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#define PPC32_SPR_TBU_WRITE 285 /* Time Base Up (write) */ |
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#define PPC32_SPR_PVR 287 /* Processor Version Register */ |
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#define PPC32_SPR_HID0 1008 |
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#define PPC32_SPR_HID1 1009 |
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#define PPC405_SPR_PID 945 /* Process Identifier */ |
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/* Exception vectors */ |
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#define PPC32_EXC_SYS_RST 0x00000100 /* System Reset */ |
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#define PPC32_EXC_MC_CHK 0x00000200 /* Machine Check */ |
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#define PPC32_EXC_DSI 0x00000300 /* Data memory access failure */ |
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#define PPC32_EXC_ISI 0x00000400 /* Instruction fetch failure */ |
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#define PPC32_EXC_EXT 0x00000500 /* External Interrupt */ |
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#define PPC32_EXC_ALIGN 0x00000600 /* Alignment */ |
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#define PPC32_EXC_PROG 0x00000700 /* FPU, Illegal instruction, ... */ |
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#define PPC32_EXC_NO_FPU 0x00000800 /* FPU unavailable */ |
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#define PPC32_EXC_DEC 0x00000900 /* Decrementer */ |
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#define PPC32_EXC_SYSCALL 0x00000C00 /* System Call */ |
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#define PPC32_EXC_TRACE 0x00000D00 /* Trace */ |
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#define PPC32_EXC_FPU_HLP 0x00000E00 /* Floating-Point Assist */ |
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/* CR0 (Condition Register Field 0) bits */ |
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#define PPC32_CR0_LT_BIT 31 |
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#define PPC32_CR0_LT (1 << PPC32_CR0_LT_BIT) /* Negative */ |
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#define PPC32_CR0_GT_BIT 30 |
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#define PPC32_CR0_GT (1 << PPC32_CR0_GT_BIT) /* Positive */ |
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#define PPC32_CR0_EQ_BIT 29 |
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#define PPC32_CR0_EQ (1 << PPC32_CR0_EQ_BIT) /* Zero */ |
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#define PPC32_CR0_SO_BIT 28 |
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#define PPC32_CR0_SO (1 << PPC32_CR0_SO_BIT) /* Summary overflow */ |
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/* XER register */ |
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#define PPC32_XER_SO_BIT 31 |
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#define PPC32_XER_SO (1 << PPC32_XER_SO_BIT) /* Summary Overflow */ |
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#define PPC32_XER_OV 0x40000000 /* Overflow */ |
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#define PPC32_XER_CA_BIT 29 |
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#define PPC32_XER_CA (1 << PPC32_XER_CA_BIT) /* Carry */ |
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#define PPC32_XER_BC_MASK 0x0000007F /* Byte cnt (lswx/stswx) */ |
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/* MSR (Machine State Register) */ |
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#define PPC32_MSR_POW_MASK 0x00060000 /* Power Management */ |
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#define PPC32_MSR_ILE 0x00010000 /* Exception Little-Endian Mode */ |
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#define PPC32_MSR_EE 0x00008000 /* External Interrupt Enable */ |
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#define PPC32_MSR_PR 0x00004000 /* Privilege Level (0=supervisor) */ |
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#define PPC32_MSR_PR_SHIFT 14 |
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#define PPC32_MSR_FP 0x00002000 /* Floating-Point Available */ |
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#define PPC32_MSR_ME 0x00001000 /* Machine Check Enable */ |
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#define PPC32_MSR_FE0 0x00000800 /* Floating-Point Exception Mode 0 */ |
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#define PPC32_MSR_SE 0x00000400 /* Single-step trace enable */ |
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#define PPC32_MSR_BE 0x00000200 /* Branch Trace Enable */ |
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#define PPC32_MSR_FE1 0x00000100 /* Floating-Point Exception Mode 1 */ |
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#define PPC32_MSR_IP 0x00000040 /* Exception Prefix */ |
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#define PPC32_MSR_IR 0x00000020 /* Instruction address translation */ |
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#define PPC32_MSR_DR 0x00000010 /* Data address translation */ |
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#define PPC32_MSR_RI 0x00000002 /* Recoverable Exception */ |
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#define PPC32_MSR_LE 0x00000001 /* Little-Endian mode enable */ |
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#define PPC32_RFI_MSR_MASK 0x87c0ff73 |
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#define PPC32_EXC_SRR1_MASK 0x0000ff73 |
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#define PPC32_EXC_MSR_MASK 0x0006ef32 |
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/* Number of BAT registers (8 for PowerPC 7448) */ |
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#define PPC32_BAT_NR 8 |
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/* Number of segment registers */ |
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#define PPC32_SR_NR 16 |
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/* Upper BAT register */ |
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#define PPC32_UBAT_BEPI_MASK 0xFFFE0000 /* Block Effective Page Index */ |
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#define PPC32_UBAT_BEPI_SHIFT 17 |
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#define PPC32_UBAT_BL_MASK 0x00001FFC /* Block Length */ |
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#define PPC32_UBAT_BL_SHIFT 2 |
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#define PPC32_UBAT_XBL_MASK 0x0001FFFC /* Block Length */ |
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#define PPC32_UBAT_XBL_SHIFT 2 |
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#define PPC32_UBAT_VS 0x00000002 /* Supervisor mode valid bit */ |
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#define PPC32_UBAT_VP 0x00000001 /* User mode valid bit */ |
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#define PPC32_UBAT_PROT_MASK (PPC32_UBAT_VS|PPC32_UBAT_VP) |
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/* Lower BAT register */ |
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#define PPC32_LBAT_BRPN_MASK 0xFFFE0000 /* Physical address */ |
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#define PPC32_LBAT_BRPN_SHIFT 17 |
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#define PPC32_LBAT_WIMG_MASK 0x00000078 /* Memory/cache access mode bits */ |
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#define PPC32_LBAT_PP_MASK 0x00000003 /* Protection bits */ |
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#define PPC32_BAT_ADDR_SHIFT 17 |
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/* Segment Descriptor */ |
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#define PPC32_SD_T 0x80000000 |
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#define PPC32_SD_KS 0x40000000 /* Supervisor-state protection key */ |
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#define PPC32_SD_KP 0x20000000 /* User-state protection key */ |
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#define PPC32_SD_N 0x10000000 /* No-execute protection bit */ |
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#define PPC32_SD_VSID_MASK 0x00FFFFFF /* Virtual Segment ID */ |
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/* SDR1 Register */ |
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#define PPC32_SDR1_HTABORG_MASK 0xFFFF0000 /* Physical base address */ |
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#define PPC32_SDR1_HTABEXT_MASK 0x0000E000 /* Extended base address */ |
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#define PPC32_SDR1_HTABMASK 0x000001FF /* Mask for page table address */ |
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#define PPC32_SDR1_HTMEXT_MASK 0x00001FFF /* Extended mask */ |
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/* Page Table Entry (PTE) size: 64-bits */ |
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#define PPC32_PTE_SIZE 8 |
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/* PTE entry (Up and Lo) */ |
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#define PPC32_PTEU_V 0x80000000 /* Valid entry */ |
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#define PPC32_PTEU_VSID_MASK 0x7FFFFF80 /* Virtual Segment ID */ |
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#define PPC32_PTEU_VSID_SHIFT 7 |
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#define PPC32_PTEU_H 0x00000040 /* Hash function */ |
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#define PPC32_PTEU_API_MASK 0x0000003F /* Abbreviated Page index */ |
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#define PPC32_PTEL_RPN_MASK 0xFFFFF000 /* Physical Page Number */ |
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#define PPC32_PTEL_XPN_MASK 0x00000C00 /* Extended Page Number (0-2) */ |
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#define PPC32_PTEL_XPN_SHIFT 9 |
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#define PPC32_PTEL_R 0x00000100 /* Referenced bit */ |
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#define PPC32_PTEL_C 0x00000080 /* Changed bit */ |
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#define PPC32_PTEL_WIMG_MASK 0x00000078 /* Mem/cache access mode bits */ |
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#define PPC32_PTEL_WIMG_SHIFT 3 |
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#define PPC32_PTEL_X_MASK 0x00000004 /* Extended Page Number (3) */ |
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#define PPC32_PTEL_X_SHIFT 2 |
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#define PPC32_PTEL_PP_MASK 0x00000003 /* Page Protection bits */ |
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/* DSISR register */ |
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#define PPC32_DSISR_NOTRANS 0x40000000 /* No valid translation */ |
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#define PPC32_DSISR_STORE 0x02000000 /* Store operation */ |
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/* PowerPC 405 TLB definitions */ |
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#define PPC405_TLBHI_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ |
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#define PPC405_TLBHI_SIZE_MASK 0x00000380 /* Page Size */ |
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#define PPC405_TLBHI_SIZE_SHIFT 7 |
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#define PPC405_TLBHI_V 0x00000040 /* Valid TLB entry */ |
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#define PPC405_TLBHI_E 0x00000020 /* Endianness */ |
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#define PPC405_TLBHI_U0 0x00000010 /* User-Defined Attribute */ |
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#define PPC405_TLBLO_RPN_MASK 0xFFFFFC00 /* Real Page Number */ |
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#define PPC405_TLBLO_EX 0x00000200 /* Execute Enable */ |
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#define PPC405_TLBLO_WR 0x00000100 /* Write Enable */ |
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#define PPC405_TLBLO_ZSEL_MASK 0x000000F0 /* Zone Select */ |
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#define PPC405_TLBLO_ZSEL_SHIFT 4 |
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#define PPC405_TLBLO_W 0x00000008 /* Write-Through */ |
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#define PPC405_TLBLO_I 0x00000004 /* Caching Inhibited */ |
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#define PPC405_TLBLO_M 0x00000002 /* Memory Coherent */ |
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#define PPC405_TLBLO_G 0x00000001 /* Guarded */ |
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/* Number of TLB entries for PPC405 */ |
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#define PPC405_TLB_ENTRIES 64 |
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struct ppc405_tlb_entry { |
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m_uint32_t tlb_hi,tlb_lo,tid; |
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}; |
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/* Memory operations */ |
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enum { |
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PPC_MEMOP_LOOKUP = 0, |
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/* Instruction fetch operation */ |
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PPC_MEMOP_IFETCH, |
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/* Load operations */ |
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PPC_MEMOP_LBZ, |
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PPC_MEMOP_LHZ, |
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PPC_MEMOP_LWZ, |
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/* Load operation with sign-extend */ |
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PPC_MEMOP_LHA, |
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/* Store operations */ |
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PPC_MEMOP_STB, |
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PPC_MEMOP_STH, |
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PPC_MEMOP_STW, |
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/* Byte-Reversed operations */ |
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PPC_MEMOP_LWBR, |
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PPC_MEMOP_STWBR, |
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/* String operations */ |
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PPC_MEMOP_LSW, |
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PPC_MEMOP_STSW, |
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/* FPU operations */ |
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PPC_MEMOP_LFD, |
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PPC_MEMOP_STFD, |
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/* ICBI - Instruction Cache Block Invalidate */ |
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PPC_MEMOP_ICBI, |
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PPC_MEMOP_MAX, |
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}; |
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/* PowerPC CPU type */ |
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typedef struct cpu_ppc cpu_ppc_t; |
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/* Memory operation function prototype */ |
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typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr, |
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u_int reg); |
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/* BAT type indexes */ |
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enum { |
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PPC32_IBAT_IDX = 0, |
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PPC32_DBAT_IDX, |
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}; |
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/* BAT register */ |
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struct ppc32_bat_reg { |
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m_uint32_t reg[2]; |
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}; |
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/* BAT register programming */ |
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struct ppc32_bat_prog { |
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int type,index; |
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m_uint32_t hi,lo; |
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}; |
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/* MTS Instruction Cache and Data Cache */ |
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#define PPC32_MTS_ICACHE PPC32_IBAT_IDX |
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#define PPC32_MTS_DCACHE PPC32_DBAT_IDX |
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/* FPU Coprocessor definition */ |
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typedef struct { |
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m_uint64_t reg[PPC32_FPU_REG_NR]; |
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}ppc_fpu_t; |
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/* Maximum number of breakpoints */ |
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#define PPC32_MAX_BREAKPOINTS 8 |
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/* PowerPC CPU definition */ |
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struct cpu_ppc { |
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/* Instruction address */ |
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m_uint32_t ia; |
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/* General Purpose registers */ |
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m_uint32_t gpr[PPC32_GPR_NR]; |
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/* Pending IRQ */ |
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volatile m_uint32_t irq_pending,irq_check; |
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/* XER, Condition Register, Link Register, Count Register */ |
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m_uint32_t xer,cr,lr,ctr,reserve; |
| 285 |
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m_uint32_t xer_ca; |
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/* MTS caches (Instruction+Data) */ |
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mts32_entry_t *mts_cache[2]; |
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/* Code page translation cache */ |
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ppc32_jit_tcb_t **exec_phys_map; |
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/* Virtual address to physical page translation */ |
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fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid, |
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m_uint32_t *phys_page); |
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/* Memory access functions */ |
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ppc_memop_fn mem_op_fn[PPC_MEMOP_MAX]; |
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/* Memory lookup function (to load ELF image,...) */ |
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void *(*mem_op_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid); |
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/* MTS slow lookup function */ |
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mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr, |
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u_int cid,u_int op_code,u_int op_size, |
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u_int op_type,m_uint64_t *data, |
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u_int *exc,mts32_entry_t *alt_entry); |
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/* IRQ counters */ |
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m_uint64_t irq_count,timer_irq_count,irq_fp_count; |
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pthread_mutex_t irq_lock; |
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/* Current and free lists of translated code blocks */ |
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ppc32_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list; |
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/* Executable page area */ |
| 317 |
|
|
void *exec_page_area; |
| 318 |
|
|
size_t exec_page_area_size; |
| 319 |
|
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size_t exec_page_count,exec_page_alloc; |
| 320 |
|
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insn_exec_page_t *exec_page_free_list; |
| 321 |
|
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insn_exec_page_t *exec_page_array; |
| 322 |
|
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|
| 323 |
|
|
/* Idle PC value */ |
| 324 |
|
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volatile m_uint32_t idle_pc; |
| 325 |
|
|
|
| 326 |
|
|
/* Timer IRQs */ |
| 327 |
|
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volatile u_int timer_irq_pending,timer_irq_armed; |
| 328 |
|
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u_int timer_irq_freq; |
| 329 |
|
|
u_int timer_irq_check_itv; |
| 330 |
|
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u_int timer_drift; |
| 331 |
|
|
|
| 332 |
|
|
/* IRQ disable flag */ |
| 333 |
|
|
volatile u_int irq_disable; |
| 334 |
|
|
|
| 335 |
|
|
/* IBAT (Instruction) and DBAT (Data) registers */ |
| 336 |
|
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struct ppc32_bat_reg bat[2][PPC32_BAT_NR]; |
| 337 |
|
|
|
| 338 |
|
|
/* Segment registers */ |
| 339 |
|
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m_uint32_t sr[PPC32_SR_NR]; |
| 340 |
|
|
|
| 341 |
|
|
/* Page Table Address */ |
| 342 |
|
|
m_uint32_t sdr1; |
| 343 |
|
|
void *sdr1_hptr; |
| 344 |
|
|
|
| 345 |
|
|
/* MSR (Machine state register) */ |
| 346 |
|
|
m_uint32_t msr; |
| 347 |
|
|
|
| 348 |
|
|
/* Interrupt Registers (SRR0/SRR1) */ |
| 349 |
|
|
m_uint32_t srr0,srr1,dsisr,dar; |
| 350 |
|
|
|
| 351 |
|
|
/* SPRG registers */ |
| 352 |
|
|
m_uint32_t sprg[4]; |
| 353 |
|
|
|
| 354 |
|
|
/* PVR (Processor Version Register) */ |
| 355 |
|
|
m_uint32_t pvr; |
| 356 |
|
|
|
| 357 |
|
|
/* Time-Base register */ |
| 358 |
|
|
m_uint64_t tb; |
| 359 |
|
|
|
| 360 |
|
|
/* Decrementer */ |
| 361 |
|
|
m_uint32_t dec; |
| 362 |
|
|
|
| 363 |
|
|
/* Hardware Implementation Dependent Registers */ |
| 364 |
|
|
m_uint32_t hid0,hid1; |
| 365 |
|
|
|
| 366 |
|
|
/* String instruction position (lswi/stswi) */ |
| 367 |
|
|
u_int sw_pos; |
| 368 |
|
|
|
| 369 |
|
|
/* PowerPC 405 TLB */ |
| 370 |
|
|
struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES]; |
| 371 |
|
|
m_uint32_t ppc405_pid; |
| 372 |
|
|
|
| 373 |
|
|
/* FPU */ |
| 374 |
|
|
ppc_fpu_t fpu; |
| 375 |
|
|
|
| 376 |
|
|
/* Generic CPU instance pointer */ |
| 377 |
|
|
cpu_gen_t *gen; |
| 378 |
|
|
|
| 379 |
|
|
/* VM instance */ |
| 380 |
|
|
vm_instance_t *vm; |
| 381 |
|
|
|
| 382 |
|
|
/* MTS cache statistics */ |
| 383 |
|
|
m_uint64_t mts_misses,mts_lookups; |
| 384 |
|
|
|
| 385 |
|
|
/* JIT flush method */ |
| 386 |
|
|
u_int jit_flush_method; |
| 387 |
|
|
|
| 388 |
|
|
/* Number of compiled pages */ |
| 389 |
|
|
u_int compiled_pages; |
| 390 |
|
|
|
| 391 |
|
|
/* Fast memory operations use */ |
| 392 |
|
|
u_int fast_memop; |
| 393 |
|
|
|
| 394 |
|
|
/* IRQ idling preemption */ |
| 395 |
|
|
u_int irq_idle_preempt[32]; |
| 396 |
|
|
|
| 397 |
|
|
/* Current exec page (non-JIT) info */ |
| 398 |
|
|
m_uint64_t njm_exec_page; |
| 399 |
|
|
mips_insn_t *njm_exec_ptr; |
| 400 |
|
|
|
| 401 |
|
|
/* Performance counter (non-JIT) */ |
| 402 |
|
|
m_uint64_t perf_counter; |
| 403 |
|
|
|
| 404 |
|
|
/* non-JIT mode instruction counter */ |
| 405 |
|
|
m_uint64_t insn_exec_count; |
| 406 |
|
|
|
| 407 |
|
|
/* Breakpoints */ |
| 408 |
|
|
m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS]; |
| 409 |
|
|
u_int breakpoints_enabled; |
| 410 |
|
|
}; |
| 411 |
|
|
|
| 412 |
|
|
/* Reset a PowerPC CPU */ |
| 413 |
|
|
int ppc32_reset(cpu_ppc_t *cpu); |
| 414 |
|
|
|
| 415 |
|
|
/* Initialize a PowerPC processor */ |
| 416 |
|
|
int ppc32_init(cpu_ppc_t *cpu); |
| 417 |
|
|
|
| 418 |
|
|
/* Delete a PowerPC processor */ |
| 419 |
|
|
void ppc32_delete(cpu_ppc_t *cpu); |
| 420 |
|
|
|
| 421 |
|
|
/* Set the processor version register (PVR) */ |
| 422 |
|
|
void ppc32_set_pvr(cpu_ppc_t *cpu,m_uint32_t pvr); |
| 423 |
|
|
|
| 424 |
|
|
/* Set idle PC value */ |
| 425 |
|
|
void ppc32_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr); |
| 426 |
|
|
|
| 427 |
|
|
/* Timer IRQ */ |
| 428 |
|
|
void *ppc32_timer_irq_run(cpu_ppc_t *cpu); |
| 429 |
|
|
|
| 430 |
|
|
/* Determine an "idling" PC */ |
| 431 |
|
|
int ppc32_get_idling_pc(cpu_gen_t *cpu); |
| 432 |
|
|
|
| 433 |
|
|
/* Generate an exception */ |
| 434 |
|
|
void ppc32_trigger_exception(cpu_ppc_t *cpu,u_int exc_vector); |
| 435 |
|
|
|
| 436 |
|
|
/* Trigger the decrementer exception */ |
| 437 |
|
|
void ppc32_trigger_timer_irq(cpu_ppc_t *cpu); |
| 438 |
|
|
|
| 439 |
|
|
/* Trigger IRQs */ |
| 440 |
|
|
fastcall void ppc32_trigger_irq(cpu_ppc_t *cpu); |
| 441 |
|
|
|
| 442 |
|
|
/* Virtual breakpoint */ |
| 443 |
|
|
fastcall void ppc32_run_breakpoint(cpu_ppc_t *cpu); |
| 444 |
|
|
|
| 445 |
|
|
/* Add a virtual breakpoint */ |
| 446 |
|
|
int ppc32_add_breakpoint(cpu_gen_t *cpu,m_uint64_t ia); |
| 447 |
|
|
|
| 448 |
|
|
/* Remove a virtual breakpoint */ |
| 449 |
|
|
void ppc32_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t ia); |
| 450 |
|
|
|
| 451 |
|
|
/* Set a register */ |
| 452 |
|
|
void ppc32_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val); |
| 453 |
|
|
|
| 454 |
|
|
/* Dump registers of a PowerPC processor */ |
| 455 |
|
|
void ppc32_dump_regs(cpu_gen_t *cpu); |
| 456 |
|
|
|
| 457 |
|
|
/* Dump MMU registers */ |
| 458 |
|
|
void ppc32_dump_mmu(cpu_gen_t *cpu); |
| 459 |
|
|
|
| 460 |
|
|
/* Load a raw image into the simulated memory */ |
| 461 |
|
|
int ppc32_load_raw_image(cpu_ppc_t *cpu,char *filename,m_uint32_t vaddr); |
| 462 |
|
|
|
| 463 |
|
|
/* Load an ELF image into the simulated memory */ |
| 464 |
|
|
int ppc32_load_elf_image(cpu_ppc_t *cpu,char *filename,int skip_load, |
| 465 |
|
|
m_uint32_t *entry_point); |
| 466 |
|
|
|
| 467 |
|
|
/* Run PowerPC code in step-by-step mode */ |
| 468 |
|
|
void *ppc32_exec_run_cpu(cpu_gen_t *gen); |
| 469 |
|
|
|
| 470 |
|
|
#endif |
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