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dpavlin |
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/* |
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* Cisco 7200 (Predator) simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* MIPS64 JIT compiler. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <unistd.h> |
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#include <string.h> |
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#include <sys/types.h> |
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#include <sys/stat.h> |
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#include <sys/mman.h> |
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#include <signal.h> |
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#include <fcntl.h> |
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#include <assert.h> |
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#include ARCH_INC_FILE |
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#include "rbtree.h" |
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#include "cp0.h" |
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#include "memory.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "mips64.h" |
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#include "mips64_exec.h" |
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#include "insn_lookup.h" |
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#include "ptask.h" |
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#if DEBUG_BLOCK_TIMESTAMP |
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static volatile m_uint64_t jit_jiffies = 0; |
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#endif |
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/* MIPS jump instructions for block scan */ |
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struct insn_jump mips64_insn_jumps[] = { |
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{ "b" , 0xffff0000, 0x10000000, 16, 1 }, |
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{ "bal" , 0xffff0000, 0x04110000, 16, 1 }, |
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{ "beq" , 0xfc000000, 0x10000000, 16, 1 }, |
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{ "beql" , 0xfc000000, 0x50000000, 16, 1 }, |
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{ "bgez" , 0xfc1f0000, 0x04010000, 16, 1 }, |
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{ "bgezl" , 0xfc1f0000, 0x04030000, 16, 1 }, |
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{ "bgezal" , 0xfc1f0000, 0x04110000, 16, 1 }, |
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{ "bgezall" , 0xfc1f0000, 0x04130000, 16, 1 }, |
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{ "bgtz" , 0xfc1f0000, 0x1c000000, 16, 1 }, |
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{ "bgtzl" , 0xfc1f0000, 0x5c000000, 16, 1 }, |
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{ "blez" , 0xfc1f0000, 0x18000000, 16, 1 }, |
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{ "blezl" , 0xfc1f0000, 0x58000000, 16, 1 }, |
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{ "bltz" , 0xfc1f0000, 0x04000000, 16, 1 }, |
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{ "bltzl" , 0xfc1f0000, 0x04020000, 16, 1 }, |
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{ "bltzal" , 0xfc1f0000, 0x04100000, 16, 1 }, |
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{ "bltzall" , 0xfc1f0000, 0x04120000, 16, 1 }, |
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{ "bne" , 0xfc000000, 0x14000000, 16, 1 }, |
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{ "bnel" , 0xfc000000, 0x54000000, 16, 1 }, |
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{ "j" , 0xfc000000, 0x08000000, 26, 0 }, |
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{ NULL , 0x00000000, 0x00000000, 0, 0 }, |
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}; |
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/* Instruction Lookup Table */ |
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static insn_lookup_t *ilt = NULL; |
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static void *mips64_jit_get_insn(int index) |
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{ |
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return(&mips64_insn_tags[index]); |
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} |
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static int mips64_jit_chk_lo(struct insn_tag *tag,int value) |
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{ |
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return((value & tag->mask) == (tag->value & 0xFFFF)); |
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} |
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static int mips64_jit_chk_hi(struct insn_tag *tag,int value) |
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{ |
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return((value & (tag->mask >> 16)) == (tag->value >> 16)); |
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} |
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/* Initialize instruction lookup table */ |
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void mips64_jit_create_ilt(void) |
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{ |
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int i,count; |
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for(i=0,count=0;mips64_insn_tags[i].emit;i++) |
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count++; |
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ilt = ilt_create(count, |
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(ilt_get_insn_cbk_t)mips64_jit_get_insn, |
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(ilt_check_cbk_t)mips64_jit_chk_lo, |
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(ilt_check_cbk_t)mips64_jit_chk_hi); |
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} |
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/* Initialize the JIT structure */ |
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int mips64_jit_init(cpu_mips_t *cpu) |
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{ |
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insn_exec_page_t *cp; |
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u_char *cp_addr; |
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u_int area_size; |
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size_t len; |
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int i; |
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/* Physical mapping for executable pages */ |
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len = 1048576 * sizeof(void *); |
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cpu->exec_phys_map = m_memalign(4096,len); |
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memset(cpu->exec_phys_map,0,len); |
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/* Get area size */ |
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if (!(area_size = cpu->vm->exec_area_size)) |
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area_size = MIPS_EXEC_AREA_SIZE; |
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/* Create executable page area */ |
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cpu->exec_page_area_size = area_size * 1048576; |
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cpu->exec_page_area = mmap(NULL,cpu->exec_page_area_size, |
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PROT_EXEC|PROT_READ|PROT_WRITE, |
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MAP_SHARED|MAP_ANONYMOUS,-1,(off_t)0); |
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if (!cpu->exec_page_area) { |
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fprintf(stderr, |
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"mips64_jit_init: unable to create exec area (size %lu)\n", |
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(u_long)cpu->exec_page_area_size); |
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return(-1); |
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} |
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/* Carve the executable page area */ |
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cpu->exec_page_count = cpu->exec_page_area_size / MIPS_JIT_BUFSIZE; |
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cpu->exec_page_array = calloc(cpu->exec_page_count, |
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sizeof(insn_exec_page_t)); |
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if (!cpu->exec_page_array) { |
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fprintf(stderr,"mips64_jit_init: unable to create exec page array\n"); |
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return(-1); |
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} |
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for(i=0,cp_addr=cpu->exec_page_area;i<cpu->exec_page_count;i++) { |
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cp = &cpu->exec_page_array[i]; |
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cp->ptr = cp_addr; |
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cp_addr += MIPS_JIT_BUFSIZE; |
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cp->next = cpu->exec_page_free_list; |
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cpu->exec_page_free_list = cp; |
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} |
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printf("CPU%u: carved JIT exec zone of %lu Mb into %lu pages of %u Kb.\n", |
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cpu->id,(u_long)(cpu->exec_page_area_size / 1048576), |
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(u_long)cpu->exec_page_count,MIPS_JIT_BUFSIZE / 1024); |
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return(0); |
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} |
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/* Flush the JIT */ |
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u_int mips64_jit_flush(cpu_mips_t *cpu,u_int threshold) |
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{ |
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insn_block_t *p,*next; |
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u_int count = 0; |
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if (!threshold) |
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threshold = (u_int)(-1); /* UINT_MAX not defined everywhere */ |
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for(p=cpu->insn_block_list;p;p=next) { |
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next = p->next; |
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if (p->acc_count <= threshold) { |
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cpu->exec_phys_map[p->phys_page] = NULL; |
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insn_block_free(cpu,p,TRUE); |
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count++; |
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} |
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} |
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cpu->compiled_pages -= count; |
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return(count); |
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} |
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/* Shutdown the JIT */ |
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void mips64_jit_shutdown(cpu_mips_t *cpu) |
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{ |
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insn_block_t *p,*next; |
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/* Flush the JIT */ |
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mips64_jit_flush(cpu,0); |
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/* Free the instruction blocks */ |
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for(p=cpu->insn_block_free_list;p;p=next) { |
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next = p->next; |
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free(p); |
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} |
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/* Unmap the executable page area */ |
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if (cpu->exec_page_area) |
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munmap(cpu->exec_page_area,cpu->exec_page_area_size); |
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/* Free the exec page array */ |
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free(cpu->exec_page_array); |
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/* Free physical mapping for executable pages */ |
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free(cpu->exec_phys_map); |
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} |
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/* Allocate an exec page */ |
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static inline insn_exec_page_t *exec_page_alloc(cpu_mips_t *cpu) |
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{ |
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insn_exec_page_t *p; |
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u_int count; |
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/* If the free list is empty, flush JIT */ |
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if (unlikely(!cpu->exec_page_free_list)) |
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{ |
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if (cpu->jit_flush_method) { |
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cpu_log(cpu,"JIT","flushing data structures (compiled pages=%u)\n", |
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cpu->compiled_pages); |
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mips64_jit_flush(cpu,0); |
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} else { |
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count = mips64_jit_flush(cpu,100); |
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cpu_log(cpu,"JIT","partial JIT flush (count=%u)\n",count); |
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if (!cpu->exec_page_free_list) |
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mips64_jit_flush(cpu,0); |
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} |
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/* Use both methods alternatively */ |
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cpu->jit_flush_method = 1 - cpu->jit_flush_method; |
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} |
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if (unlikely(!(p = cpu->exec_page_free_list))) |
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return NULL; |
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cpu->exec_page_free_list = p->next; |
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cpu->exec_page_alloc++; |
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return p; |
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} |
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/* Free an exec page and returns it to the pool */ |
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static inline void exec_page_free(cpu_mips_t *cpu,insn_exec_page_t *p) |
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{ |
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if (p) { |
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p->next = cpu->exec_page_free_list; |
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cpu->exec_page_free_list = p; |
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cpu->exec_page_alloc--; |
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} |
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} |
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/* Find the JIT code emitter for the specified MIPS instruction */ |
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struct insn_tag *insn_tag_find(mips_insn_t ins) |
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{ |
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struct insn_tag *tag = NULL; |
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int index; |
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index = ilt_lookup(ilt,ins); |
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tag = mips64_jit_get_insn(index); |
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return tag; |
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} |
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/* Check if the specified MIPS instruction is a jump */ |
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struct insn_jump *insn_jump_find(mips_insn_t ins) |
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{ |
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struct insn_jump *jump = NULL; |
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int i; |
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for(i=0;mips64_insn_jumps[i].name;i++) |
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if ((ins & mips64_insn_jumps[i].mask) == mips64_insn_jumps[i].value) { |
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jump = &mips64_insn_jumps[i]; |
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break; |
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} |
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return(jump); |
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} |
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/* Fetch a MIPS instruction */ |
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static forced_inline mips_insn_t insn_fetch(insn_block_t *b) |
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{ |
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return(vmtoh32(b->mips_code[b->mips_trans_pos])); |
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} |
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/* Emit a breakpoint if necessary */ |
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#if BREAKPOINT_ENABLE |
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static void insn_emit_breakpoint(cpu_mips_t *cpu,insn_block_t *b) |
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{ |
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m_uint64_t pc; |
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int i; |
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pc = b->start_pc+((b->mips_trans_pos-1)<<2); |
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for(i=0;i<MIPS64_MAX_BREAKPOINTS;i++) |
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if (pc == cpu->breakpoints[i]) { |
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mips64_emit_breakpoint(b); |
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break; |
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} |
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} |
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#endif /* BREAKPOINT_ENABLE */ |
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/* Fetch a MIPS instruction and emit corresponding translated code */ |
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struct insn_tag *insn_fetch_and_emit(cpu_mips_t *cpu,insn_block_t *block, |
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int delay_slot) |
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{ |
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struct insn_tag *tag; |
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mips_insn_t code; |
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code = insn_fetch(block); |
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tag = insn_tag_find(code); |
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assert(tag); |
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300 |
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if (delay_slot && !tag->delay_slot) { |
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mips64_emit_invalid_delay_slot(block); |
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return NULL; |
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} |
304 |
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305 |
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if (!delay_slot) { |
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block->jit_insn_ptr[block->mips_trans_pos] = block->jit_ptr; |
307 |
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} |
308 |
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309 |
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if (delay_slot != 2) |
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block->mips_trans_pos++; |
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312 |
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#if DEBUG_PERF_COUNTER |
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mips64_inc_perf_counter(block); |
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#endif |
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316 |
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if (!delay_slot) { |
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/* Check for IRQs + Increment count register before jumps */ |
318 |
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if (!tag->delay_slot) { |
319 |
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mips64_inc_cp0_count_reg(block); |
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mips64_check_pending_irq(block); |
321 |
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} |
322 |
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} |
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324 |
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#if BREAKPOINT_ENABLE |
325 |
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if (cpu->breakpoints_enabled) |
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insn_emit_breakpoint(cpu,block); |
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#endif |
328 |
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329 |
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tag->emit(cpu,block,code); |
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return tag; |
331 |
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} |
332 |
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333 |
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/* Add end of JIT block */ |
334 |
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void insn_block_add_end(insn_block_t *b) |
335 |
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{ |
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mips64_set_pc(b,b->start_pc+(b->mips_trans_pos<<2)); |
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insn_block_push_epilog(b); |
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} |
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340 |
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/* Record a patch to apply in a compiled block */ |
341 |
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int insn_block_record_patch(insn_block_t *block,u_char *jit_ptr, |
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m_uint64_t vaddr) |
343 |
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{ |
344 |
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struct insn_patch_table *ipt = block->patch_table; |
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struct insn_patch *patch; |
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/* pc must be 32-bit aligned */ |
348 |
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if (vaddr & 0x03) { |
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fprintf(stderr,"Block 0x%8.8llx: trying to record an invalid PC " |
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"(0x%8.8llx) - mips_trans_pos=%d.\n", |
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block->start_pc,vaddr,block->mips_trans_pos); |
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return(-1); |
353 |
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} |
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355 |
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if (!ipt || (ipt->cur_patch >= INSN_PATCH_TABLE_SIZE)) |
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{ |
357 |
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/* full table or no table, create a new one */ |
358 |
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ipt = malloc(sizeof(*ipt)); |
359 |
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if (!ipt) { |
360 |
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fprintf(stderr,"%% Unable to create patch table.\n"); |
361 |
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return(-1); |
362 |
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} |
363 |
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364 |
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memset(ipt,0,sizeof(*ipt)); |
365 |
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ipt->next = block->patch_table; |
366 |
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block->patch_table = ipt; |
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} |
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#if DEBUG_BLOCK_PATCH |
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printf("Block 0x%8.8llx: recording patch [JIT:%p->mips:0x%8.8llx], " |
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"MTP=%d\n",block->start_pc,jit_ptr,vaddr,block->mips_trans_pos); |
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#endif |
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374 |
|
|
patch = &ipt->patches[ipt->cur_patch]; |
375 |
|
|
patch->jit_insn = jit_ptr; |
376 |
|
|
patch->mips_pc = vaddr; |
377 |
|
|
ipt->cur_patch++; |
378 |
|
|
return(0); |
379 |
|
|
} |
380 |
|
|
|
381 |
|
|
/* Apply all patches */ |
382 |
|
|
int insn_block_apply_patches(cpu_mips_t *cpu,insn_block_t *block) |
383 |
|
|
{ |
384 |
|
|
struct insn_patch_table *ipt; |
385 |
|
|
struct insn_patch *patch; |
386 |
|
|
u_char *jit_dst; |
387 |
|
|
int i; |
388 |
|
|
|
389 |
|
|
for(ipt=block->patch_table;ipt;ipt=ipt->next) |
390 |
|
|
for(i=0;i<ipt->cur_patch;i++) |
391 |
|
|
{ |
392 |
|
|
patch = &ipt->patches[i]; |
393 |
|
|
jit_dst = insn_block_get_jit_ptr(block,patch->mips_pc); |
394 |
|
|
|
395 |
|
|
if (jit_dst) { |
396 |
|
|
#if DEBUG_BLOCK_PATCH |
397 |
|
|
printf("Block 0x%8.8llx: applying patch " |
398 |
|
|
"[JIT:%p->mips:0x%8.8llx=JIT:%p]\n", |
399 |
|
|
block->start_pc,patch->jit_insn,patch->mips_pc,jit_dst); |
400 |
|
|
#endif |
401 |
|
|
insn_block_set_patch(patch->jit_insn,jit_dst); |
402 |
|
|
} |
403 |
|
|
} |
404 |
|
|
|
405 |
|
|
return(0); |
406 |
|
|
} |
407 |
|
|
|
408 |
|
|
/* Free the patch table */ |
409 |
|
|
static void insn_block_free_patches(insn_block_t *block) |
410 |
|
|
{ |
411 |
|
|
struct insn_patch_table *p,*next; |
412 |
|
|
|
413 |
|
|
for(p=block->patch_table;p;p=next) { |
414 |
|
|
next = p->next; |
415 |
|
|
free(p); |
416 |
|
|
} |
417 |
|
|
|
418 |
|
|
block->patch_table = NULL; |
419 |
|
|
} |
420 |
|
|
|
421 |
|
|
/* Adjust the JIT buffer if its size is not sufficient */ |
422 |
|
|
int insn_block_adjust_jit_buffer(cpu_mips_t *cpu,insn_block_t *block) |
423 |
|
|
{ |
424 |
|
|
insn_exec_page_t *new_buffer; |
425 |
|
|
|
426 |
|
|
if ((block->jit_ptr - block->jit_buffer->ptr) <= (MIPS_JIT_BUFSIZE - 512)) |
427 |
|
|
return(0); |
428 |
|
|
|
429 |
|
|
#if DEBUG_BLOCK_CHUNK |
430 |
|
|
printf("Block 0x%llx: adjusting JIT buffer...\n",block->start_pc); |
431 |
|
|
#endif |
432 |
|
|
|
433 |
|
|
if (block->jit_chunk_pos >= INSN_MAX_CHUNKS) { |
434 |
|
|
fprintf(stderr,"Block 0x%llx: too many JIT chunks.\n",block->start_pc); |
435 |
|
|
return(-1); |
436 |
|
|
} |
437 |
|
|
|
438 |
|
|
if (!(new_buffer = exec_page_alloc(cpu))) |
439 |
|
|
return(-1); |
440 |
|
|
|
441 |
|
|
/* record the new exec page */ |
442 |
|
|
block->jit_chunks[block->jit_chunk_pos++] = block->jit_buffer; |
443 |
|
|
block->jit_buffer = new_buffer; |
444 |
|
|
|
445 |
|
|
/* jump to the new exec page (link) */ |
446 |
|
|
insn_block_set_jump(block->jit_ptr,new_buffer->ptr); |
447 |
|
|
block->jit_ptr = new_buffer->ptr; |
448 |
|
|
return(0); |
449 |
|
|
} |
450 |
|
|
|
451 |
|
|
/* Allocate an instruction block */ |
452 |
|
|
static inline insn_block_t *insn_block_alloc(cpu_mips_t *cpu) |
453 |
|
|
{ |
454 |
|
|
insn_block_t *p; |
455 |
|
|
|
456 |
|
|
if (cpu->insn_block_free_list) { |
457 |
|
|
p = cpu->insn_block_free_list; |
458 |
|
|
cpu->insn_block_free_list = p->next; |
459 |
|
|
} else { |
460 |
|
|
if (!(p = malloc(sizeof(*p)))) |
461 |
|
|
return NULL; |
462 |
|
|
} |
463 |
|
|
|
464 |
|
|
memset(p,0,sizeof(*p)); |
465 |
|
|
return p; |
466 |
|
|
} |
467 |
|
|
|
468 |
|
|
/* Free an instruction block */ |
469 |
|
|
void insn_block_free(cpu_mips_t *cpu,insn_block_t *block,int list_removal) |
470 |
|
|
{ |
471 |
|
|
int i; |
472 |
|
|
|
473 |
|
|
if (block) { |
474 |
|
|
if (list_removal) { |
475 |
|
|
/* Remove the block from the linked list */ |
476 |
|
|
if (block->next) |
477 |
|
|
block->next->prev = block->prev; |
478 |
|
|
else |
479 |
|
|
cpu->insn_block_last = block->prev; |
480 |
|
|
|
481 |
|
|
if (block->prev) |
482 |
|
|
block->prev->next = block->next; |
483 |
|
|
else |
484 |
|
|
cpu->insn_block_list = block->next; |
485 |
|
|
} |
486 |
|
|
|
487 |
|
|
/* Free the patch tables */ |
488 |
|
|
insn_block_free_patches(block); |
489 |
|
|
|
490 |
|
|
/* Free code pages */ |
491 |
|
|
for(i=0;i<INSN_MAX_CHUNKS;i++) |
492 |
|
|
exec_page_free(cpu,block->jit_chunks[i]); |
493 |
|
|
|
494 |
|
|
/* Free the current JIT buffer */ |
495 |
|
|
exec_page_free(cpu,block->jit_buffer); |
496 |
|
|
|
497 |
|
|
/* Free the MIPS-to-native code mapping */ |
498 |
|
|
free(block->jit_insn_ptr); |
499 |
|
|
|
500 |
|
|
/* Make the block return to the free list */ |
501 |
|
|
block->next = cpu->insn_block_free_list; |
502 |
|
|
cpu->insn_block_free_list = block; |
503 |
|
|
} |
504 |
|
|
} |
505 |
|
|
|
506 |
|
|
/* Create an instruction block */ |
507 |
|
|
static insn_block_t *insn_block_create(cpu_mips_t *cpu,m_uint64_t vaddr) |
508 |
|
|
{ |
509 |
|
|
insn_block_t *block = NULL; |
510 |
|
|
|
511 |
|
|
if (!(block = insn_block_alloc(cpu))) |
512 |
|
|
goto err_block_alloc; |
513 |
|
|
|
514 |
|
|
block->start_pc = vaddr; |
515 |
|
|
|
516 |
|
|
/* Allocate the first JIT buffer */ |
517 |
|
|
if (!(block->jit_buffer = exec_page_alloc(cpu))) |
518 |
|
|
goto err_jit_alloc; |
519 |
|
|
|
520 |
|
|
block->jit_ptr = block->jit_buffer->ptr; |
521 |
|
|
block->mips_code = cpu->mem_op_lookup(cpu,block->start_pc); |
522 |
|
|
|
523 |
|
|
if (!block->mips_code) { |
524 |
|
|
fprintf(stderr,"%% No memory map for code execution at 0x%llx\n", |
525 |
|
|
block->start_pc); |
526 |
|
|
goto err_lookup; |
527 |
|
|
} |
528 |
|
|
|
529 |
|
|
#if DEBUG_BLOCK_TIMESTAMP |
530 |
|
|
block->tm_first_use = block->tm_last_use = jit_jiffies; |
531 |
|
|
#endif |
532 |
|
|
return block; |
533 |
|
|
|
534 |
|
|
err_lookup: |
535 |
|
|
err_jit_alloc: |
536 |
|
|
insn_block_free(cpu,block,FALSE); |
537 |
|
|
err_block_alloc: |
538 |
|
|
fprintf(stderr,"%% Unable to create instruction block for vaddr=0x%llx\n", |
539 |
|
|
vaddr); |
540 |
|
|
return NULL; |
541 |
|
|
} |
542 |
|
|
|
543 |
|
|
/* Compile a MIPS instruction page */ |
544 |
|
|
static inline insn_block_t *insn_page_compile(cpu_mips_t *cpu,m_uint64_t vaddr) |
545 |
|
|
{ |
546 |
|
|
m_uint64_t page_addr; |
547 |
|
|
insn_block_t *block; |
548 |
|
|
struct insn_tag *tag; |
549 |
|
|
size_t len; |
550 |
|
|
|
551 |
|
|
page_addr = vaddr & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK; |
552 |
|
|
|
553 |
|
|
if (unlikely(!(block = insn_block_create(cpu,page_addr)))) { |
554 |
|
|
fprintf(stderr,"insn_page_compile: unable to create JIT block.\n"); |
555 |
|
|
return NULL; |
556 |
|
|
} |
557 |
|
|
|
558 |
|
|
/* Allocate the array used to convert MIPS code ptr to native code ptr */ |
559 |
|
|
len = MIPS_MIN_PAGE_SIZE / sizeof(mips_insn_t); |
560 |
|
|
|
561 |
|
|
if (!(block->jit_insn_ptr = calloc(len,sizeof(u_char *)))) { |
562 |
|
|
fprintf(stderr,"insn_page_compile: unable to create JIT mappings.\n"); |
563 |
|
|
goto error; |
564 |
|
|
} |
565 |
|
|
|
566 |
|
|
/* Emit native code for each instruction */ |
567 |
|
|
block->mips_trans_pos = 0; |
568 |
|
|
|
569 |
|
|
while(block->mips_trans_pos < (MIPS_MIN_PAGE_SIZE/sizeof(mips_insn_t))) |
570 |
|
|
{ |
571 |
|
|
if (unlikely(!(tag = insn_fetch_and_emit(cpu,block,0)))) { |
572 |
|
|
fprintf(stderr,"insn_page_compile: unable to fetch instruction.\n"); |
573 |
|
|
goto error; |
574 |
|
|
} |
575 |
|
|
|
576 |
|
|
#if DEBUG_BLOCK_COMPILE |
577 |
|
|
printf("Page 0x%8.8llx: emitted tag 0x%8.8x/0x%8.8x\n", |
578 |
|
|
block->start_pc,tag->mask,tag->value); |
579 |
|
|
#endif |
580 |
|
|
|
581 |
|
|
insn_block_adjust_jit_buffer(cpu,block); |
582 |
|
|
} |
583 |
|
|
|
584 |
|
|
insn_block_add_end(block); |
585 |
|
|
insn_block_apply_patches(cpu,block); |
586 |
|
|
insn_block_free_patches(block); |
587 |
|
|
|
588 |
|
|
/* Add the block to the linked list */ |
589 |
|
|
block->next = cpu->insn_block_list; |
590 |
|
|
block->prev = NULL; |
591 |
|
|
|
592 |
|
|
if (cpu->insn_block_list) |
593 |
|
|
cpu->insn_block_list->prev = block; |
594 |
|
|
else |
595 |
|
|
cpu->insn_block_last = block; |
596 |
|
|
|
597 |
|
|
cpu->insn_block_list = block; |
598 |
|
|
|
599 |
|
|
cpu->compiled_pages++; |
600 |
|
|
return block; |
601 |
|
|
|
602 |
|
|
error: |
603 |
|
|
insn_block_free(cpu,block,FALSE); |
604 |
|
|
return NULL; |
605 |
|
|
} |
606 |
|
|
|
607 |
|
|
/* Run a compiled MIPS instruction block */ |
608 |
|
|
static forced_inline void insn_block_run(cpu_mips_t *cpu,insn_block_t *block) |
609 |
|
|
{ |
610 |
|
|
#if DEBUG_SYM_TREE |
611 |
|
|
struct symbol *sym = NULL; |
612 |
|
|
int mark = FALSE; |
613 |
|
|
#endif |
614 |
|
|
|
615 |
|
|
if (unlikely(cpu->pc & 0x03)) { |
616 |
|
|
fprintf(stderr,"insn_block_run: Invalid PC 0x%llx.\n",cpu->pc); |
617 |
|
|
mips64_dump_regs(cpu); |
618 |
|
|
tlb_dump(cpu); |
619 |
|
|
cpu_stop(cpu); |
620 |
|
|
return; |
621 |
|
|
} |
622 |
|
|
|
623 |
|
|
#if DEBUG_SYM_TREE |
624 |
|
|
if (cpu->sym_trace && cpu->sym_tree) |
625 |
|
|
{ |
626 |
|
|
if ((sym = mips64_sym_lookup(cpu,cpu->pc)) != NULL) { |
627 |
|
|
cpu_log(cpu,"insn_block_run(start)", |
628 |
|
|
"%s (PC=0x%llx) RA = 0x%llx\na0=0x%llx, " |
629 |
|
|
"a1=0x%llx, a2=0x%llx, a3=0x%llx\n", |
630 |
|
|
sym->name, cpu->pc, cpu->gpr[MIPS_GPR_RA], |
631 |
|
|
cpu->gpr[MIPS_GPR_A0], cpu->gpr[MIPS_GPR_A1], |
632 |
|
|
cpu->gpr[MIPS_GPR_A2], cpu->gpr[MIPS_GPR_A3]); |
633 |
|
|
mark = TRUE; |
634 |
|
|
} |
635 |
|
|
} |
636 |
|
|
#endif |
637 |
|
|
|
638 |
|
|
/* Execute JIT compiled code */ |
639 |
|
|
insn_block_exec_jit_code(cpu,block); |
640 |
|
|
|
641 |
|
|
#if DEBUG_SYM_TREE |
642 |
|
|
if (mark) { |
643 |
|
|
cpu_log(cpu,"insn_block_run(end)","%s, v0 = 0x%llx\n", |
644 |
|
|
sym->name,cpu->gpr[MIPS_GPR_V0]); |
645 |
|
|
} |
646 |
|
|
#endif |
647 |
|
|
} |
648 |
|
|
|
649 |
|
|
/* Check if the specified address belongs to the specified block */ |
650 |
|
|
int insn_block_local_addr(insn_block_t *block,m_uint64_t vaddr, |
651 |
|
|
u_char **jit_addr) |
652 |
|
|
{ |
653 |
|
|
if ((vaddr >= block->start_pc) && |
654 |
|
|
((vaddr - block->start_pc) < MIPS_MIN_PAGE_SIZE)) |
655 |
|
|
{ |
656 |
|
|
*jit_addr = insn_block_get_jit_ptr(block,vaddr); |
657 |
|
|
return(1); |
658 |
|
|
} |
659 |
|
|
|
660 |
|
|
return(0); |
661 |
|
|
} |
662 |
|
|
|
663 |
dpavlin |
2 |
/* Check if PC register matches the compiled block virtual address */ |
664 |
|
|
static forced_inline int insn_block_match(cpu_mips_t *cpu,insn_block_t *block) |
665 |
|
|
{ |
666 |
|
|
m_uint64_t vpage; |
667 |
|
|
|
668 |
|
|
vpage = cpu->pc & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK; |
669 |
|
|
return(block->start_pc == vpage); |
670 |
|
|
} |
671 |
|
|
|
672 |
dpavlin |
1 |
/* Execute a compiled MIPS code */ |
673 |
|
|
void *insn_block_execute(cpu_mips_t *cpu) |
674 |
|
|
{ |
675 |
|
|
pthread_t timer_irq_thread; |
676 |
|
|
insn_block_t *block; |
677 |
|
|
m_uint32_t phys_page; |
678 |
|
|
int timer_irq_check = 0; |
679 |
|
|
|
680 |
|
|
if (pthread_create(&timer_irq_thread,NULL, |
681 |
|
|
(void *)mips64_timer_irq_run,cpu)) |
682 |
|
|
{ |
683 |
|
|
fprintf(stderr,"VM '%s': unable to create Timer IRQ thread for CPU%u.\n", |
684 |
|
|
cpu->vm->name,cpu->id); |
685 |
|
|
cpu_stop(cpu); |
686 |
|
|
return NULL; |
687 |
|
|
} |
688 |
|
|
|
689 |
|
|
cpu->cpu_thread_running = TRUE; |
690 |
dpavlin |
3 |
|
691 |
dpavlin |
1 |
start_cpu: |
692 |
dpavlin |
3 |
cpu->idle_count = 0; |
693 |
|
|
|
694 |
dpavlin |
1 |
for(;;) { |
695 |
dpavlin |
2 |
if (unlikely(cpu->state != MIPS_CPU_RUNNING)) |
696 |
dpavlin |
1 |
break; |
697 |
|
|
|
698 |
|
|
/* Handle virtual idle loop */ |
699 |
|
|
if (unlikely(cpu->pc == cpu->idle_pc)) { |
700 |
dpavlin |
3 |
if (++cpu->idle_count == cpu->idle_max) { |
701 |
dpavlin |
1 |
mips64_idle_loop(cpu); |
702 |
dpavlin |
3 |
cpu->idle_count = 0; |
703 |
dpavlin |
1 |
} |
704 |
|
|
} |
705 |
|
|
|
706 |
|
|
/* Handle the virtual CPU clock */ |
707 |
|
|
if (++timer_irq_check == cpu->timer_irq_check_itv) { |
708 |
|
|
timer_irq_check = 0; |
709 |
|
|
|
710 |
|
|
if (cpu->timer_irq_pending && !cpu->irq_disable) { |
711 |
|
|
mips64_trigger_timer_irq(cpu); |
712 |
|
|
mips64_trigger_irq(cpu); |
713 |
|
|
cpu->timer_irq_pending--; |
714 |
|
|
} |
715 |
|
|
} |
716 |
|
|
|
717 |
|
|
/* Get the physical page address corresponding to PC register */ |
718 |
|
|
if (unlikely(cpu->translate(cpu,cpu->pc,&phys_page))) { |
719 |
|
|
fprintf(stderr,"VM '%s': no physical page for CPU%u PC=0x%llx\n", |
720 |
|
|
cpu->vm->name,cpu->id,cpu->pc); |
721 |
|
|
cpu_stop(cpu); |
722 |
|
|
break; |
723 |
|
|
} |
724 |
|
|
|
725 |
|
|
block = cpu->exec_phys_map[phys_page]; |
726 |
|
|
|
727 |
|
|
/* No block found, compile the page */ |
728 |
dpavlin |
2 |
if (unlikely(!block) || unlikely(!insn_block_match(cpu,block))) |
729 |
|
|
{ |
730 |
|
|
if (block != NULL) { |
731 |
|
|
insn_block_free(cpu,block,TRUE); |
732 |
|
|
cpu->exec_phys_map[phys_page] = NULL; |
733 |
|
|
} |
734 |
|
|
|
735 |
dpavlin |
1 |
block = insn_page_compile(cpu,cpu->pc); |
736 |
|
|
if (unlikely(!block)) { |
737 |
|
|
fprintf(stderr, |
738 |
|
|
"VM '%s': unable to compile block for CPU%u PC=0x%llx\n", |
739 |
|
|
cpu->vm->name,cpu->id,cpu->pc); |
740 |
|
|
cpu_stop(cpu); |
741 |
|
|
break; |
742 |
|
|
} |
743 |
|
|
|
744 |
|
|
block->phys_page = phys_page; |
745 |
|
|
cpu->exec_phys_map[phys_page] = block; |
746 |
|
|
} |
747 |
|
|
|
748 |
|
|
#if DEBUG_BLOCK_TIMESTAMP |
749 |
|
|
block->tm_last_use = jit_jiffies++; |
750 |
|
|
#endif |
751 |
|
|
block->acc_count++; |
752 |
|
|
insn_block_run(cpu,block); |
753 |
|
|
} |
754 |
|
|
|
755 |
|
|
if (!cpu->pc) { |
756 |
|
|
cpu_stop(cpu); |
757 |
|
|
cpu_log(cpu,"JIT","PC=0, halting CPU.\n"); |
758 |
|
|
} |
759 |
|
|
|
760 |
|
|
/* Check regularly if the CPU has been restarted */ |
761 |
|
|
while(cpu->cpu_thread_running) { |
762 |
|
|
cpu->seq_state++; |
763 |
|
|
|
764 |
|
|
switch(cpu->state) { |
765 |
|
|
case MIPS_CPU_RUNNING: |
766 |
|
|
cpu->state = MIPS_CPU_RUNNING; |
767 |
|
|
goto start_cpu; |
768 |
|
|
|
769 |
|
|
case MIPS_CPU_HALTED: |
770 |
|
|
cpu->cpu_thread_running = FALSE; |
771 |
|
|
pthread_join(timer_irq_thread,NULL); |
772 |
|
|
break; |
773 |
|
|
} |
774 |
|
|
|
775 |
|
|
/* CPU is paused */ |
776 |
|
|
usleep(200000); |
777 |
|
|
} |
778 |
|
|
|
779 |
|
|
return NULL; |
780 |
|
|
} |