/[dynamips]/upstream/dynamips-0.2.7-RC1/dev_pa_a1.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_pa_a1.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_pa_a1.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*    /*  
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * PA-A1 ATM interface based on TI1570 and PLX 9060-ES.   * PA-A1 ATM interface based on TI1570 and PLX 9060-ES.
# Line 35  Line 35 
35    
36  #include "crc.h"  #include "crc.h"
37  #include "atm.h"  #include "atm.h"
38  #include "mips64.h"  #include "cpu.h"
39    #include "vm.h"
40  #include "dynamips.h"  #include "dynamips.h"
41  #include "memory.h"  #include "memory.h"
42  #include "device.h"  #include "device.h"
# Line 338  static void ti1570_reset(struct pa_a1_da Line 339  static void ti1570_reset(struct pa_a1_da
339  /*  /*
340   * dev_pa_a1_access()   * dev_pa_a1_access()
341   */   */
342  void *dev_pa_a1_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_pa_a1_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
343                         u_int op_size,u_int op_type,m_uint64_t *data)                         u_int op_size,u_int op_type,m_uint64_t *data)
344  {  {
345     struct pa_a1_data *d = dev->priv_data;     struct pa_a1_data *d = dev->priv_data;
# Line 349  void *dev_pa_a1_access(cpu_mips_t *cpu,s Line 350  void *dev_pa_a1_access(cpu_mips_t *cpu,s
350  #if DEBUG_ACCESS  #if DEBUG_ACCESS
351     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
352        cpu_log(cpu,"TI1570","read  access to offset = 0x%x, pc = 0x%llx\n",        cpu_log(cpu,"TI1570","read  access to offset = 0x%x, pc = 0x%llx\n",
353                offset,cpu->pc);                offset,cpu_get_pc(cpu));
354     } else {     } else {
355        cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, "
356                "val = 0x%llx\n",offset,cpu->pc,*data);                "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
357     }     }
358  #endif    #endif  
359    
# Line 384  void *dev_pa_a1_access(cpu_mips_t *cpu,s Line 385  void *dev_pa_a1_access(cpu_mips_t *cpu,s
385  #if DEBUG_UNKNOWN  #if DEBUG_UNKNOWN
386     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
387        cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",        cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
388                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
389     } else {     } else {
390        cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, "        cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, "
391                "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                "pc=0x%llx (size=%u)\n",offset,*data,cpu_get_pc(cpu),op_size);
392     }     }
393  #endif  #endif
394     return NULL;     return NULL;
# Line 1428  static int ti1570_handle_rx_cell(netio_d Line 1429  static int ti1570_handle_rx_cell(netio_d
1429  /*  /*
1430   * pci_ti1570_read()   * pci_ti1570_read()
1431   */   */
1432  static m_uint32_t pci_ti1570_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_ti1570_read(cpu_gen_t *cpu,struct pci_device *dev,
1433                                    int reg)                                    int reg)
1434  {  {
1435     struct pa_a1_data *d = dev->priv_data;     struct pa_a1_data *d = dev->priv_data;
# Line 1448  static m_uint32_t pci_ti1570_read(cpu_mi Line 1449  static m_uint32_t pci_ti1570_read(cpu_mi
1449  /*  /*
1450   * pci_ti1570_write()   * pci_ti1570_write()
1451   */   */
1452  static void pci_ti1570_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_ti1570_write(cpu_gen_t *cpu,struct pci_device *dev,
1453                               int reg,m_uint32_t value)                               int reg,m_uint32_t value)
1454  {  {
1455     struct pa_a1_data *d = dev->priv_data;     struct pa_a1_data *d = dev->priv_data;
# Line 1468  static void pci_ti1570_write(cpu_mips_t Line 1469  static void pci_ti1570_write(cpu_mips_t
1469  /*  /*
1470   * pci_plx9060es_read()   * pci_plx9060es_read()
1471   */   */
1472  static m_uint32_t pci_plx9060es_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_plx9060es_read(cpu_gen_t *cpu,struct pci_device *dev,
1473                                       int reg)                                       int reg)
1474  {  {
1475  #if DEBUG_ACCESS  #if DEBUG_ACCESS
# Line 1483  static m_uint32_t pci_plx9060es_read(cpu Line 1484  static m_uint32_t pci_plx9060es_read(cpu
1484  /*  /*
1485   * pci_plx9060es_write()   * pci_plx9060es_write()
1486   */   */
1487  static void pci_plx9060es_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_plx9060es_write(cpu_gen_t *cpu,struct pci_device *dev,
1488                                  int reg,m_uint32_t value)                                  int reg,m_uint32_t value)
1489  {  {
1490  #if DEBUG_ACCESS  #if DEBUG_ACCESS

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