/[dynamips]/upstream/dynamips-0.2.7-RC1/dev_c7200_iofpga.c
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Annotation of /upstream/dynamips-0.2.7-RC1/dev_c7200_iofpga.c

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Revision 5 - (hide annotations)
Sat Oct 6 16:08:03 2007 UTC (12 years, 2 months ago) by dpavlin
Original Path: upstream/dynamips-0.2.6-RC4/dev_c7200_iofpga.c
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File size: 17988 byte(s)
dynamips-0.2.6-RC4

1 dpavlin 1 /*
2     * Cisco 7200 (Predator) simulation platform.
3     * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4     *
5     * Cisco C7200 (Predator) I/O FPGA:
6     * - Simulates a NMC93C46 Serial EEPROM as CPU and Midplane EEPROM.
7     * - Simulates a DALLAS DS1620 for Temperature Sensors.
8     * - Simulates voltage sensors.
9     * - Simulates console and AUX ports.
10     */
11    
12     #include <stdio.h>
13     #include <stdlib.h>
14     #include <string.h>
15     #include <unistd.h>
16     #include <sys/types.h>
17    
18     #include <termios.h>
19     #include <fcntl.h>
20     #include <pthread.h>
21    
22     #include "ptask.h"
23     #include "mips64.h"
24     #include "dynamips.h"
25     #include "memory.h"
26     #include "device.h"
27     #include "dev_vtty.h"
28     #include "nmc93c46.h"
29     #include "ds1620.h"
30     #include "dev_c7200.h"
31    
32     /* Debugging flags */
33     #define DEBUG_UNKNOWN 1
34     #define DEBUG_ACCESS 0
35     #define DEBUG_LED 0
36     #define DEBUG_IO_CTL 0
37     #define DEBUG_ENVM 0
38    
39     /* DUART RX/TX status (SRA/SRB) */
40     #define DUART_RX_READY 0x01
41     #define DUART_TX_READY 0x04
42    
43     /* DUART RX/TX Interrupt Status/Mask */
44     #define DUART_TXRDYA 0x01
45     #define DUART_RXRDYA 0x02
46     #define DUART_TXRDYB 0x10
47     #define DUART_RXRDYB 0x20
48    
49     /* Definitions for CPU and Midplane Serial EEPROMs */
50     #define DO2_DATA_OUT_MIDPLANE 7
51     #define DO1_DATA_OUT_CPU 6
52     #define CS2_CHIP_SEL_MIDPLANE 5
53     #define SK2_CLOCK_MIDPLANE 4
54     #define DI2_DATA_IN_MIDPLANE 3
55     #define CS1_CHIP_SEL_CPU 2
56     #define SK1_CLOCK_CPU 1
57     #define DI1_DATA_IN_CPU 0
58    
59     /* Definitions for PEM (NPE-B) Serial EEPROM */
60     #define DO1_DATA_OUT_PEM 3
61     #define DI1_DATA_IN_PEM 2
62     #define CS1_CHIP_SEL_PEM 1
63     #define SK1_CLOCK_PEM 0
64    
65     /* Pack the NVRAM */
66     #define NVRAM_PACKED 0x04
67    
68     /* 4 temperature sensors in a C7200 */
69     #define C7200_TEMP_SENSORS 4
70     #define C7200_DEFAULT_TEMP 22 /* default temperature: 22°C */
71    
72     /* Voltages */
73     #define C7200_A2D_SAMPLES 9
74    
75     /*
76     * A2D MUX Select definitions.
77     */
78     #define C7200_MUX_PS0 0x00 /* Power Supply 0 */
79     #define C7200_MUX_PS1 0x02 /* Power Supply 1 */
80     #define C7200_MUX_P3V 0x04 /* +3V */
81     #define C7200_MUX_P12V 0x08 /* +12V */
82     #define C7200_MUX_P5V 0x0a /* +5V */
83     #define C7200_MUX_N12V 0x0c /* -12V */
84    
85     /* Analog To Digital Converters samples */
86     #define C7200_A2D_PS0 1150
87     #define C7200_A2D_PS1 1150
88    
89     /* Voltage Samples */
90     #define C7200_A2D_P3V 1150
91     #define C7200_A2D_P12V 1150
92     #define C7200_A2D_P5V 1150
93     #define C7200_A2D_N12V 1150
94    
95     /* IO FPGA structure */
96     struct iofpga_data {
97     vm_obj_t vm_obj;
98     struct vdevice dev;
99     c7200_t *router;
100    
101     /* Lock test */
102     pthread_mutex_t lock;
103    
104     /* Periodic task to trigger dummy DUART IRQ */
105     ptask_id_t duart_irq_tid;
106    
107     /* DUART & Console Management */
108     u_int duart_isr,duart_imr,duart_irq_seq;
109    
110     /* IO control register */
111     u_int io_ctrl_reg;
112    
113     /* Temperature Control */
114     u_int temp_cfg_reg[C7200_TEMP_SENSORS];
115     u_int temp_deg_reg[C7200_TEMP_SENSORS];
116     u_int temp_clk_low;
117    
118     u_int temp_cmd;
119     u_int temp_cmd_pos;
120    
121     u_int temp_data;
122     u_int temp_data_pos;
123    
124     /* Voltages */
125     u_int mux;
126     };
127    
128     #define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock)
129     #define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock)
130    
131     /* CPU EEPROM definition */
132     static const struct nmc93c46_eeprom_def eeprom_cpu_def = {
133     SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU,
134     DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU,
135     };
136    
137     /* Midplane EEPROM definition */
138     static const struct nmc93c46_eeprom_def eeprom_midplane_def = {
139     SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE,
140     DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE,
141     };
142    
143     /* PEM (NPE-B) EEPROM definition */
144     static const struct nmc93c46_eeprom_def eeprom_pem_def = {
145     SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM,
146     };
147    
148     /* IOFPGA manages simultaneously CPU and Midplane EEPROM */
149     static const struct nmc93c46_group eeprom_cpu_midplane = {
150     2, 0, "CPU and Midplane EEPROM", 0,
151 dpavlin 3 { &eeprom_cpu_def, &eeprom_midplane_def },
152 dpavlin 1 };
153    
154     /*
155     * IOFPGA manages also PEM EEPROM (for NPE-B)
156     * PEM stands for "Power Entry Module":
157     * http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml
158     */
159     static const struct nmc93c46_group eeprom_pem_npeb = {
160 dpavlin 3 1, 0, "PEM (NPE-B) EEPROM", 0, { &eeprom_pem_def },
161 dpavlin 1 };
162    
163     /* Reset DS1620 */
164     static void temp_reset(struct iofpga_data *d)
165     {
166     d->temp_cmd_pos = 0;
167     d->temp_cmd = 0;
168    
169     d->temp_data_pos = 0;
170     d->temp_data = 0;
171     }
172    
173     /* Write the temperature control data */
174     static void temp_write_ctrl(struct iofpga_data *d,u_char val)
175     {
176     switch(val) {
177     case DS1620_RESET_ON:
178     temp_reset(d);
179     break;
180    
181     case DS1620_CLK_LOW:
182     d->temp_clk_low = 1;
183     break;
184    
185     case DS1620_CLK_HIGH:
186     d->temp_clk_low = 0;
187     break;
188     }
189     }
190    
191     /* Read a temperature control data */
192     static u_int temp_read_data(struct iofpga_data *d)
193     {
194     u_int i,data = 0;
195    
196     switch(d->temp_cmd) {
197     case DS1620_READ_CONFIG:
198     for(i=0;i<C7200_TEMP_SENSORS;i++)
199     data |= ((d->temp_cfg_reg[i] >> d->temp_data_pos) & 1) << i;
200    
201     d->temp_data_pos++;
202    
203     if (d->temp_data_pos == DS1620_CONFIG_READ_SIZE)
204     temp_reset(d);
205    
206     break;
207    
208     case DS1620_READ_TEMP:
209     for(i=0;i<C7200_TEMP_SENSORS;i++)
210     data |= ((d->temp_deg_reg[i] >> d->temp_data_pos) & 1) << i;
211    
212     d->temp_data_pos++;
213    
214     if (d->temp_data_pos == DS1620_DATA_READ_SIZE)
215     temp_reset(d);
216    
217     break;
218    
219     default:
220     vm_log(d->router->vm,"IO_FPGA","temp_sensors: CMD = 0x%x\n",
221     d->temp_cmd);
222     }
223    
224     return(data);
225     }
226    
227     /* Write the temperature data write register */
228     static void temp_write_data(struct iofpga_data *d,u_char val)
229     {
230     if (val == DS1620_ENABLE_READ) {
231     d->temp_data_pos = 0;
232     return;
233     }
234    
235     if (!d->temp_clk_low)
236     return;
237    
238     /* Write a command */
239     if (d->temp_cmd_pos < DS1620_WRITE_SIZE)
240     {
241     if (val == DS1620_DATA_HIGH)
242     d->temp_cmd |= 1 << d->temp_cmd_pos;
243    
244     d->temp_cmd_pos++;
245    
246     if (d->temp_cmd_pos == DS1620_WRITE_SIZE) {
247     switch(d->temp_cmd) {
248     case DS1620_START_CONVT:
249     //printf("temp_sensors: IOS enabled continuous monitoring.\n");
250     temp_reset(d);
251     break;
252     case DS1620_READ_CONFIG:
253     case DS1620_READ_TEMP:
254     break;
255     default:
256     vm_log(d->router->vm,"IO_FPGA",
257     "temp_sensors: IOS sent command 0x%x.\n",
258     d->temp_cmd);
259     }
260     }
261     }
262     else
263     {
264     if (val == DS1620_DATA_HIGH)
265     d->temp_data |= 1 << d->temp_data_pos;
266    
267     d->temp_data_pos++;
268     }
269     }
270    
271     /* Console port input */
272     static void tty_con_input(vtty_t *vtty)
273     {
274     struct iofpga_data *d = vtty->priv_data;
275    
276     IOFPGA_LOCK(d);
277     if (d->duart_imr & DUART_RXRDYA) {
278     d->duart_isr |= DUART_RXRDYA;
279     vm_set_irq(d->router->vm,C7200_DUART_IRQ);
280     }
281     IOFPGA_UNLOCK(d);
282     }
283    
284     /* AUX port input */
285     static void tty_aux_input(vtty_t *vtty)
286     {
287     struct iofpga_data *d = vtty->priv_data;
288    
289     IOFPGA_LOCK(d);
290     if (d->duart_imr & DUART_RXRDYB) {
291     d->duart_isr |= DUART_RXRDYB;
292     vm_set_irq(d->router->vm,C7200_DUART_IRQ);
293     }
294     IOFPGA_UNLOCK(d);
295     }
296    
297     /* IRQ trickery for Console and AUX ports */
298     static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg)
299     {
300     u_int mask;
301    
302     IOFPGA_LOCK(d);
303     d->duart_irq_seq++;
304    
305     if (d->duart_irq_seq == 2) {
306     mask = DUART_TXRDYA|DUART_TXRDYB;
307     if (d->duart_imr & mask) {
308     d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB;
309     vm_set_irq(d->router->vm,C7200_DUART_IRQ);
310     }
311    
312     d->duart_irq_seq = 0;
313     }
314    
315     IOFPGA_UNLOCK(d);
316     return(0);
317     }
318    
319     /*
320     * dev_c7200_iofpga_access()
321     */
322     void *dev_c7200_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev,
323     m_uint32_t offset,u_int op_size,u_int op_type,
324     m_uint64_t *data)
325     {
326     struct iofpga_data *d = dev->priv_data;
327     vm_instance_t *vm = d->router->vm;
328     u_char odata;
329    
330     if (op_type == MTS_READ)
331     *data = 0x0;
332    
333     #if DEBUG_ACCESS
334     if (op_type == MTS_READ) {
335     cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n",offset,cpu->pc);
336     } else {
337     cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n",
338     offset,cpu->pc,*data);
339     }
340     #endif
341    
342     IOFPGA_LOCK(d);
343    
344     switch(offset) {
345     case 0x294:
346     /*
347     * Unknown, seen in 12.4(6)T, and seems to be read at each
348     * network interrupt.
349     */
350     if (op_type == MTS_READ)
351     *data = 0x0;
352     break;
353    
354     /* NPE-G1 test - unknown (value written: 0x01) */
355     case 0x338:
356     break;
357    
358     /* NPE-G1 test - has influence on slot 0 / flash / pcmcia ... */
359     case 0x390:
360     if (op_type == MTS_READ)
361     *data = 0x0FFF0000; //0xFFFF0000;
362     break;
363    
364     /* I/O control register */
365     case 0x204:
366     if (op_type == MTS_WRITE) {
367     #if DEBUG_IO_CTL
368     vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data);
369     #endif
370     d->io_ctrl_reg = *data;
371     }
372     else {
373     *data = d->io_ctrl_reg;
374     *data |= NVRAM_PACKED; /* Packed NVRAM */
375     }
376     break;
377    
378     /* CPU/Midplane EEPROMs */
379     case 0x21c:
380     if (op_type == MTS_WRITE)
381     nmc93c46_write(&d->router->sys_eeprom_g1,(u_int)(*data));
382     else
383     *data = nmc93c46_read(&d->router->sys_eeprom_g1);
384     break;
385    
386     /* PEM (NPE-B) EEPROM */
387     case 0x388:
388     if (op_type == MTS_WRITE)
389     nmc93c46_write(&d->router->sys_eeprom_g2,(u_int)(*data));
390     else
391     *data = nmc93c46_read(&d->router->sys_eeprom_g2);
392     break;
393    
394     /* Watchdog */
395     case 0x234:
396     break;
397    
398     /*
399     * FPGA release/presence ? Flash SIMM size:
400     * 0x0001: 2048K Flash (2 banks)
401     * 0x0504: 8192K Flash (2 banks)
402     * 0x0704: 16384K Flash (2 banks)
403     * 0x0904: 32768K Flash (2 banks)
404     * 0x0B04: 65536K Flash (2 banks)
405     * 0x2001: 1024K Flash (1 bank)
406     * 0x2504: 4096K Flash (1 bank)
407     * 0x2704: 8192K Flash (1 bank)
408     * 0x2904: 16384K Flash (1 bank)
409     * 0x2B04: 32768K Flash (1 bank)
410     *
411     * Number of Flash SIMM banks + size.
412     * Touching some lower bits causes problems with environmental monitor.
413     *
414     * It is displayed by command "sh bootflash: chips"
415     */
416     case 0x23c:
417     if (op_type == MTS_READ)
418     *data = 0x2704;
419     break;
420    
421     /* LEDs */
422     case 0x244:
423     #if DEBUG_LED
424     vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n",
425     *data,(~*data) & 0x0F);
426     #endif
427     break;
428    
429     /* ==== DUART SCN2681 (console/aux) ==== */
430     case 0x404: /* Mode Register A (MRA) */
431     break;
432    
433     case 0x40c: /* Status Register A (SRA) */
434     if (op_type == MTS_READ) {
435     odata = 0;
436    
437     if (vtty_is_char_avail(vm->vtty_con))
438     odata |= DUART_RX_READY;
439    
440     odata |= DUART_TX_READY;
441    
442     vm_clear_irq(vm,C7200_DUART_IRQ);
443     *data = odata;
444     }
445     break;
446    
447     case 0x414: /* Command Register A (CRA) */
448     /* Disable TX = High */
449     if ((op_type == MTS_WRITE) && (*data & 0x8)) {
450     vm->vtty_con->managed_flush = TRUE;
451     vtty_flush(vm->vtty_con);
452     }
453     break;
454    
455     case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */
456     if (op_type == MTS_WRITE) {
457     vtty_put_char(vm->vtty_con,(char)*data);
458     d->duart_isr &= ~DUART_TXRDYA;
459     } else {
460     *data = vtty_get_char(vm->vtty_con);
461     d->duart_isr &= ~DUART_RXRDYA;
462     }
463     break;
464    
465     case 0x424: /* WRITE: Aux Control Register (ACR) */
466     break;
467    
468     case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */
469     if (op_type == MTS_WRITE) {
470     d->duart_imr = *data;
471     } else
472     *data = d->duart_isr;
473     break;
474    
475     case 0x434: /* Counter/Timer Upper Value (CTU) */
476     case 0x43c: /* Counter/Timer Lower Value (CTL) */
477     case 0x444: /* Mode Register B (MRB) */
478     break;
479    
480     case 0x44c: /* Status Register B (SRB) */
481     if (op_type == MTS_READ) {
482     odata = 0;
483    
484     if (vtty_is_char_avail(vm->vtty_aux))
485     odata |= DUART_RX_READY;
486    
487     odata |= DUART_TX_READY;
488    
489     //vm_clear_irq(vm,C7200_DUART_IRQ);
490     *data = odata;
491     }
492     break;
493    
494     case 0x454: /* Command Register B (CRB) */
495     /* Disable TX = High */
496     if ((op_type == MTS_WRITE) && (*data & 0x8)) {
497     vm->vtty_aux->managed_flush = TRUE;
498     vtty_flush(vm->vtty_aux);
499     }
500     break;
501    
502     case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */
503     if (op_type == MTS_WRITE) {
504     vtty_put_char(vm->vtty_aux,(char)*data);
505     d->duart_isr &= ~DUART_TXRDYA;
506     } else {
507     *data = vtty_get_char(vm->vtty_aux);
508     d->duart_isr &= ~DUART_RXRDYB;
509     }
510     break;
511    
512     case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */
513     case 0x474: /* READ: Start Counter Command; */
514     /* WRITE: Set Output Port Bits Command */
515     case 0x47c: /* WRITE: Reset Output Port Bits Command */
516     break;
517    
518     /* ==== DS 1620 (temp sensors) ==== */
519     case 0x20c: /* Temperature Control */
520     if (op_type == MTS_WRITE)
521     temp_write_ctrl(d,*data);
522     break;
523    
524     case 0x214: /* Temperature data write */
525     if (op_type == MTS_WRITE) {
526     temp_write_data(d,*data);
527     d->mux = *data;
528     }
529     break;
530    
531     case 0x22c: /* Temperature data read */
532     if (op_type == MTS_READ)
533     *data = temp_read_data(d);
534     break;
535    
536     /*
537     * NPE-G1 - Voltages + Power Supplies.
538     * I don't understand exactly how it works, it seems that the low
539     * part must be equal to the high part to have the better values.
540     */
541     case 0x254:
542     #if DEBUG_ENVM
543     vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
544     #endif
545     if (op_type == MTS_READ)
546     *data = 0xFFFFFFFF;
547     break;
548    
549     case 0x257: /* ENVM A/D Converter */
550     #if DEBUG_ENVM
551     vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
552     #endif
553     if (op_type == MTS_READ) {
554     switch(d->mux) {
555     case C7200_MUX_PS0:
556     *data = C7200_A2D_PS0;
557     break;
558    
559     case C7200_MUX_PS1:
560     *data = C7200_A2D_PS1;
561     break;
562    
563     case C7200_MUX_P3V:
564     *data = C7200_A2D_P3V;
565     break;
566    
567     case C7200_MUX_P12V:
568     *data = C7200_A2D_P12V;
569     break;
570    
571     case C7200_MUX_P5V:
572     *data = C7200_A2D_P5V;
573     break;
574    
575     case C7200_MUX_N12V:
576     *data = C7200_A2D_N12V;
577     break;
578    
579     default:
580     *data = 0;
581     }
582    
583     *data = *data / C7200_A2D_SAMPLES;
584     }
585     break;
586    
587     #if DEBUG_UNKNOWN
588     default:
589     if (op_type == MTS_READ) {
590     cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n",
591     offset,cpu->pc,op_size);
592     } else {
593     cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, "
594     "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);
595     }
596     #endif
597     }
598    
599     IOFPGA_UNLOCK(d);
600     return NULL;
601     }
602    
603     /* Initialize EEPROM groups */
604     void c7200_init_eeprom_groups(c7200_t *router)
605     {
606 dpavlin 3 router->sys_eeprom_g1 = eeprom_cpu_midplane;
607     router->sys_eeprom_g2 = eeprom_pem_npeb;
608 dpavlin 1
609 dpavlin 3 router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom;
610     router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom;
611 dpavlin 1
612 dpavlin 3 router->sys_eeprom_g2.eeprom[0] = &router->pem_eeprom;
613 dpavlin 1 }
614    
615     /* Shutdown the IO FPGA device */
616     void dev_c7200_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d)
617     {
618     if (d != NULL) {
619     IOFPGA_LOCK(d);
620     vm->vtty_con->read_notifier = NULL;
621     vm->vtty_aux->read_notifier = NULL;
622     IOFPGA_UNLOCK(d);
623    
624     /* Remove the dummy IRQ periodic task */
625     ptask_remove(d->duart_irq_tid);
626    
627     /* Remove the device */
628     dev_remove(vm,&d->dev);
629    
630     /* Free the structure itself */
631     free(d);
632     }
633     }
634    
635     /*
636     * dev_c7200_iofpga_init()
637     */
638     int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len)
639     {
640     vm_instance_t *vm = router->vm;
641     struct iofpga_data *d;
642     u_int i;
643    
644     /* Allocate private data structure */
645     if (!(d = malloc(sizeof(*d)))) {
646     fprintf(stderr,"IO_FPGA: out of memory\n");
647     return(-1);
648     }
649    
650     memset(d,0,sizeof(*d));
651    
652     pthread_mutex_init(&d->lock,NULL);
653     d->router = router;
654    
655     for(i=0;i<C7200_TEMP_SENSORS;i++) {
656     d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU;
657     d->temp_deg_reg[i] = C7200_DEFAULT_TEMP * 2;
658     }
659    
660     vm_object_init(&d->vm_obj);
661     d->vm_obj.name = "io_fpga";
662     d->vm_obj.data = d;
663     d->vm_obj.shutdown = (vm_shutdown_t)dev_c7200_iofpga_shutdown;
664    
665     /* Set device properties */
666     dev_init(&d->dev);
667     d->dev.name = "io_fpga";
668     d->dev.phys_addr = paddr;
669     d->dev.phys_len = len;
670     d->dev.handler = dev_c7200_iofpga_access;
671     d->dev.priv_data = d;
672    
673     /* Set console and AUX port notifying functions */
674     vm->vtty_con->priv_data = d;
675     vm->vtty_aux->priv_data = d;
676     vm->vtty_con->read_notifier = tty_con_input;
677     vm->vtty_aux->read_notifier = tty_aux_input;
678    
679     /* Trigger periodically a dummy IRQ to flush buffers */
680     d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,d,NULL);
681    
682     /* Map this device to the VM */
683     vm_bind_device(vm,&d->dev);
684     vm_object_add(vm,&d->vm_obj);
685     return(0);
686     }

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