/[dynamips]/upstream/dynamips-0.2.7-RC1/dev_c3725_iofpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /upstream/dynamips-0.2.7-RC1/dev_c3725_iofpga.c

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upstream/dynamips-0.2.6-RC5/dev_c3725_iofpga.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c3725_iofpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 15  Line 15 
15  #include <pthread.h>  #include <pthread.h>
16    
17  #include "ptask.h"  #include "ptask.h"
18  #include "mips64.h"  #include "cpu.h"
19    #include "vm.h"
20  #include "dynamips.h"  #include "dynamips.h"
21  #include "memory.h"  #include "memory.h"
22  #include "device.h"  #include "device.h"
# Line 87  static const struct nmc93c46_group eepro Line 88  static const struct nmc93c46_group eepro
88   * dev_c3725_iofpga_access()   * dev_c3725_iofpga_access()
89   */   */
90  static void *  static void *
91  dev_c3725_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev,  dev_c3725_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
92                          m_uint32_t offset,u_int op_size,u_int op_type,                          m_uint32_t offset,u_int op_size,u_int op_type,
93                          m_uint64_t *data)                          m_uint64_t *data)
94  {  {
# Line 99  dev_c3725_iofpga_access(cpu_mips_t *cpu, Line 100  dev_c3725_iofpga_access(cpu_mips_t *cpu,
100  #if DEBUG_ACCESS  #if DEBUG_ACCESS
101     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
102        cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",        cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
103                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
104     } else {     } else {
105        cpu_log(cpu,"IO_FPGA",        cpu_log(cpu,"IO_FPGA",
106                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
107                offset,cpu->pc,*data,op_size);                offset,cpu_get_pc(cpu),*data,op_size);
108     }     }
109  #endif  #endif
110    
# Line 294  dev_c3725_iofpga_access(cpu_mips_t *cpu, Line 295  dev_c3725_iofpga_access(cpu_mips_t *cpu,
295           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
296              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
297                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
298                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
299           } else {           } else {
300              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
301                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
302                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
303                        offset,*data,cpu_get_pc(cpu),op_size);
304           }           }
305  #endif  #endif
306     }     }
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