/[dynamips]/upstream/dynamips-0.2.6-RC3/mips64.h
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Annotation of /upstream/dynamips-0.2.6-RC3/mips64.h

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Revision 1 - (hide annotations)
Sat Oct 6 16:01:44 2007 UTC (12 years, 2 months ago) by dpavlin
Original Path: upstream/dynamips-0.2.5/mips64.h
File MIME type: text/plain
File size: 19908 byte(s)
import 0.2.5 from upstream

1 dpavlin 1 /*
2     * Cisco 7200 (Predator) simulation platform.
3     * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4     */
5    
6     #ifndef __MIPS_64_H__
7     #define __MIPS_64_H__
8    
9     #include <pthread.h>
10    
11     #include "utils.h"
12     #include "rbtree.h"
13    
14     /*
15     * MIPS General Purpose Registers
16     */
17     #define MIPS_GPR_ZERO 0 /* zero */
18     #define MIPS_GPR_AT 1 /* at */
19     #define MIPS_GPR_V0 2 /* v0 */
20     #define MIPS_GPR_V1 3 /* v1 */
21     #define MIPS_GPR_A0 4 /* a0 */
22     #define MIPS_GPR_A1 5 /* a1 */
23     #define MIPS_GPR_A2 6 /* a2 */
24     #define MIPS_GPR_A3 7 /* a3 */
25     #define MIPS_GPR_T0 8 /* t0 */
26     #define MIPS_GPR_T1 9 /* t1 */
27     #define MIPS_GPR_T2 10 /* t2 */
28     #define MIPS_GPR_T3 11 /* t3 */
29     #define MIPS_GPR_T4 12 /* t4 */
30     #define MIPS_GPR_T5 13 /* t5 */
31     #define MIPS_GPR_T6 14 /* t6 */
32     #define MIPS_GPR_T7 15 /* t7 */
33     #define MIPS_GPR_S0 16 /* s0 */
34     #define MIPS_GPR_S1 17 /* s1 */
35     #define MIPS_GPR_S2 18 /* s2 */
36     #define MIPS_GPR_S3 19 /* s3 */
37     #define MIPS_GPR_S4 20 /* s4 */
38     #define MIPS_GPR_S5 21 /* s5 */
39     #define MIPS_GPR_S6 22 /* s6 */
40     #define MIPS_GPR_S7 23 /* s7 */
41     #define MIPS_GPR_T8 24 /* t8 */
42     #define MIPS_GPR_T9 25 /* t9 */
43     #define MIPS_GPR_K0 26 /* k0 */
44     #define MIPS_GPR_K1 27 /* k1 */
45     #define MIPS_GPR_GP 28 /* gp */
46     #define MIPS_GPR_SP 29 /* sp */
47     #define MIPS_GPR_FP 30 /* fp */
48     #define MIPS_GPR_RA 31 /* ra */
49    
50     /*
51     * Coprocessor 0 (System Coprocessor) Register definitions
52     */
53     #define MIPS_CP0_INDEX 0 /* TLB Index */
54     #define MIPS_CP0_RANDOM 1 /* TLB Random */
55     #define MIPS_CP0_TLB_LO_0 2 /* TLB Entry Lo0 */
56     #define MIPS_CP0_TLB_LO_1 3 /* TLB Entry Lo1 */
57     #define MIPS_CP0_CONTEXT 4 /* Kernel PTE pointer */
58     #define MIPS_CP0_PAGEMASK 5 /* TLB Page Mask */
59     #define MIPS_CP0_WIRED 6 /* TLB Wired */
60     #define MIPS_CP0_INFO 7 /* Info (RM7000) */
61     #define MIPS_CP0_BADVADDR 8 /* Bad Virtual Address */
62     #define MIPS_CP0_COUNT 9 /* Count */
63     #define MIPS_CP0_TLB_HI 10 /* TLB Entry Hi */
64     #define MIPS_CP0_COMPARE 11 /* Timer Compare */
65     #define MIPS_CP0_STATUS 12 /* Status */
66     #define MIPS_CP0_CAUSE 13 /* Cause */
67     #define MIPS_CP0_EPC 14 /* Exception PC */
68     #define MIPS_CP0_PRID 15 /* Proc Rev ID */
69     #define MIPS_CP0_CONFIG 16 /* Configuration */
70     #define MIPS_CP0_LLADDR 17 /* Load/Link address */
71     #define MIPS_CP0_WATCHLO 18 /* Low Watch address */
72     #define MIPS_CP0_WATCHHI 19 /* High Watch address */
73     #define MIPS_CP0_XCONTEXT 20 /* Extended context */
74     #define MIPS_CP0_ECC 26 /* ECC and parity */
75     #define MIPS_CP0_CACHERR 27 /* Cache Err/Status */
76     #define MIPS_CP0_TAGLO 28 /* Cache Tag Lo */
77     #define MIPS_CP0_TAGHI 29 /* Cache Tag Hi */
78     #define MIPS_CP0_ERR_EPC 30 /* Error exception PC */
79    
80     /*
81     * CP0 Set 1 Registers (R7000)
82     */
83     #define MIPS_CP0_S1_CONFIG 16 /* Configuration Register */
84     #define MIPS_CP0_S1_IPLLO 18 /* Priority level for IRQ [7:0] */
85     #define MIPS_CP0_S1_IPLHI 19 /* Priority level for IRQ [15:8] */
86     #define MIPS_CP0_S1_INTCTL 20 /* Interrupt Control */
87     #define MIPS_CP0_S1_DERRADDR0 26 /* Imprecise Error Address */
88     #define MIPS_CP0_S1_DERRADDR1 27 /* Imprecise Error Address */
89    
90     /*
91     * CP0 Status Register
92     */
93     #define MIPS_CP0_STATUS_CU0 0x10000000
94     #define MIPS_CP0_STATUS_CU1 0x20000000
95     #define MIPS_CP0_STATUS_BEV 0x00400000
96     #define MIPS_CP0_STATUS_TS 0x00200000
97     #define MIPS_CP0_STATUS_SR 0x00100000
98     #define MIPS_CP0_STATUS_CH 0x00040000
99     #define MIPS_CP0_STATUS_CE 0x00020000
100     #define MIPS_CP0_STATUS_DE 0x00010000
101     #define MIPS_CP0_STATUS_RP 0x08000000
102     #define MIPS_CP0_STATUS_FR 0x04000000
103     #define MIPS_CP0_STATUS_RE 0x02000000
104     #define MIPS_CP0_STATUS_KX 0x00000080
105     #define MIPS_CP0_STATUS_SX 0x00000040
106     #define MIPS_CP0_STATUS_UX 0x00000020
107     #define MIPS_CP0_STATUS_KSU 0x00000018
108     #define MIPS_CP0_STATUS_ERL 0x00000004
109     #define MIPS_CP0_STATUS_EXL 0x00000002
110     #define MIPS_CP0_STATUS_IE 0x00000001
111     #define MIPS_CP0_STATUS_IMASK7 0x00008000
112     #define MIPS_CP0_STATUS_IMASK6 0x00004000
113     #define MIPS_CP0_STATUS_IMASK5 0x00002000
114     #define MIPS_CP0_STATUS_IMASK4 0x00001000
115     #define MIPS_CP0_STATUS_IMASK3 0x00000800
116     #define MIPS_CP0_STATUS_IMASK2 0x00000400
117     #define MIPS_CP0_STATUS_IMASK1 0x00000200
118     #define MIPS_CP0_STATUS_IMASK0 0x00000100
119    
120     #define MIPS_CP0_STATUS_DS_MASK 0x00770000
121     #define MIPS_CP0_STATUS_CU_MASK 0xF0000000
122     #define MIPS_CP0_STATUS_IMASK 0x0000FF00
123    
124     /* Addressing mode: Kernel, Supervisor and User */
125     #define MIPS_CP0_STATUS_KSU_SHIFT 0x03
126     #define MIPS_CP0_STATUS_KSU_MASK 0x03
127    
128     #define MIPS_CP0_STATUS_KM 0x00
129     #define MIPS_CP0_STATUS_SM 0x01
130     #define MIPS_CP0_STATUS_UM 0x10
131    
132    
133     /*
134     * CP0 Cause register
135     */
136     #define MIPS_CP0_CAUSE_BD_SLOT 0x80000000
137    
138     #define MIPS_CP0_CAUSE_MASK 0x0000007C
139     #define MIPS_CP0_CAUSE_CEMASK 0x30000000
140     #define MIPS_CP0_CAUSE_IMASK 0x0000FF00
141    
142     #define MIPS_CP0_CAUSE_SHIFT 2
143     #define MIPS_CP0_CAUSE_CESHIFT 28
144     #define MIPS_CP0_CAUSE_ISHIFT 8
145    
146     #define MIPS_CP0_CAUSE_INTERRUPT 0
147     #define MIPS_CP0_CAUSE_TLB_MOD 1
148     #define MIPS_CP0_CAUSE_TLB_LOAD 2
149     #define MIPS_CP0_CAUSE_TLB_SAVE 3
150     #define MIPS_CP0_CAUSE_ADDR_LOAD 4 /* ADEL */
151     #define MIPS_CP0_CAUSE_ADDR_SAVE 5 /* ADES */
152     #define MIPS_CP0_CAUSE_BUS_INSTR 6
153     #define MIPS_CP0_CAUSE_BUS_DATA 7
154     #define MIPS_CP0_CAUSE_SYSCALL 8
155     #define MIPS_CP0_CAUSE_BP 9
156     #define MIPS_CP0_CAUSE_ILLOP 10
157     #define MIPS_CP0_CAUSE_CP_UNUSABLE 11
158     #define MIPS_CP0_CAUSE_OVFLW 12
159     #define MIPS_CP0_CAUSE_TRAP 13
160     #define MIPS_CP0_CAUSE_VC_INSTR 14 /* Virtual Coherency */
161     #define MIPS_CP0_CAUSE_FPE 15
162     #define MIPS_CP0_CAUSE_WATCH 23
163     #define MIPS_CP0_CAUSE_VC_DATA 31 /* Virtual Coherency */
164    
165     #define MIPS_CP0_CAUSE_IBIT7 0x00008000
166     #define MIPS_CP0_CAUSE_IBIT6 0x00004000
167     #define MIPS_CP0_CAUSE_IBIT5 0x00002000
168     #define MIPS_CP0_CAUSE_IBIT4 0x00001000
169     #define MIPS_CP0_CAUSE_IBIT3 0x00000800
170     #define MIPS_CP0_CAUSE_IBIT2 0x00000400
171     #define MIPS_CP0_CAUSE_IBIT1 0x00000200
172     #define MIPS_CP0_CAUSE_IBIT0 0x00000100
173    
174    
175     /* TLB masks and shifts */
176     #define MIPS_TLB_PAGE_MASK 0x01ffe000
177     #define MIPS_TLB_PAGE_SHIFT 13
178     #define MIPS_TLB_VPN2_MASK 0xffffffffffffe000ULL
179     #define MIPS_TLB_PFN_MASK 0x3fffffc0
180     #define MIPS_TLB_ASID_MASK 0x000000ff /* "asid" in EntryHi */
181     #define MIPS_TLB_G_MASK 0x00001000 /* "Global" in EntryHi */
182     #define MIPS_TLB_V_MASK 0x2 /* "Valid" in EntryLo */
183     #define MIPS_TLB_D_MASK 0x4 /* "Dirty" in EntryLo */
184     #define MIPS_TLB_C_MASK 0x38 /* Page Coherency Attribute */
185     #define MIPS_TLB_C_SHIFT 3
186    
187     #define MIPS_CP0_LO_G_MASK 0x00000001 /* "Global" in Lo0/1 reg */
188     #define MIPS_CP0_HI_SAFE_MASK 0xffffe0ff /* Safety mask for Hi reg */
189     #define MIPS_CP0_LO_SAFE_MASK 0x7fffffff /* Safety mask for Lo reg */
190    
191     /* MIPS "jr ra" instruction */
192     #define MIPS_INSN_JR_RA 0x03e00008
193    
194     /* Minimum page size: 4 Kb */
195     #define MIPS_MIN_PAGE_SHIFT 12
196     #define MIPS_MIN_PAGE_SIZE (1 << MIPS_MIN_PAGE_SHIFT)
197     #define MIPS_MIN_PAGE_IMASK (MIPS_MIN_PAGE_SIZE - 1)
198    
199     /* Addressing mode: Kernel, Supervisor and User */
200     #define MIPS_MODE_KERNEL 00
201    
202     /* Segments in 32-bit User mode */
203     #define MIPS_USEG_BASE 0x00000000
204     #define MIPS_USEG_SIZE 0x80000000
205    
206     /* Segments in 32-bit Supervisor mode */
207     #define MIPS_SUSEG_BASE 0x00000000
208     #define MIPS_SUSEG_SIZE 0x80000000
209     #define MIPS_SSEG_BASE 0xc0000000
210     #define MIPS_SSEG_SIZE 0x20000000
211    
212     /* Segments in 32-bit Kernel mode */
213     #define MIPS_KUSEG_BASE 0x00000000
214     #define MIPS_KUSEG_SIZE 0x80000000
215    
216     #define MIPS_KSEG0_BASE 0x80000000
217     #define MIPS_KSEG0_SIZE 0x20000000
218    
219     #define MIPS_KSEG1_BASE 0xa0000000
220     #define MIPS_KSEG1_SIZE 0x20000000
221    
222     #define MIPS_KSSEG_BASE 0xc0000000
223     #define MIPS_KSSEG_SIZE 0x20000000
224    
225     #define MIPS_KSEG3_BASE 0xe0000000
226     #define MIPS_KSEG3_SIZE 0x20000000
227    
228     /* xkphys mask (36-bit physical address) */
229     #define MIPS64_XKPHYS_ZONE_MASK 0xF800000000000000ULL
230     #define MIPS64_XKPHYS_PHYS_SIZE (1ULL << 36)
231     #define MIPS64_XKPHYS_PHYS_MASK (MIPS64_XKPHYS_PHYS_SIZE - 1)
232     #define MIPS64_XKPHYS_CCA_SHIFT 59
233    
234     /* Macros for CPU structure access */
235     #define REG_OFFSET(reg) (OFFSET(cpu_mips_t,gpr[(reg)]))
236     #define CP0_REG_OFFSET(c0reg) (OFFSET(cpu_mips_t,cp0.reg[(c0reg)]))
237     #define MEMOP_OFFSET(op) (OFFSET(cpu_mips_t,mem_op_fn[(op)]))
238    
239     /* Initial Program Counter and Stack pointer for ROM */
240     #define MIPS_ROM_PC 0xffffffffbfc00000ULL
241     #define MIPS_ROM_SP 0xffffffff80004000ULL
242    
243     /* Number of GPR (general purpose registers) */
244     #define MIPS64_GPR_NR 32
245    
246     /* Number of registers in CP0 */
247     #define MIPS64_CP0_REG_NR 32
248    
249     /* Number of registers in CP1 */
250     #define MIPS64_CP1_REG_NR 32
251    
252     /* Number of TLB entries */
253     #define MIPS64_TLB_STD_ENTRIES 48
254     #define MIPS64_TLB_MAX_ENTRIES 64
255     #define MIPS64_TLB_IDX_MASK 0x3f /* 6 bits */
256    
257     /* Enable the 64 TLB entries for R7000 CPU */
258     #define MIPS64_R7000_TLB64_ENABLE 0x20000000
259    
260     /* MIPS CPU Identifiers */
261     #define MIPS_PRID_R4600 0x00002012
262     #define MIPS_PRID_R4700 0x00002112
263     #define MIPS_PRID_R5000 0x00002312
264     #define MIPS_PRID_R7000 0x00002721
265     #define MIPS_PRID_R527x 0x00002812
266     #define MIPS_PRID_BCM1250 0x00040102
267    
268     /* Virtual CPU states */
269     enum {
270     MIPS_CPU_RUNNING = 0,
271     MIPS_CPU_HALTED,
272     MIPS_CPU_SUSPENDED,
273     };
274    
275     /* Memory operations */
276     enum {
277     MIPS_MEMOP_LOOKUP = 0,
278    
279     MIPS_MEMOP_LB,
280     MIPS_MEMOP_LBU,
281     MIPS_MEMOP_LH,
282     MIPS_MEMOP_LHU,
283     MIPS_MEMOP_LW,
284     MIPS_MEMOP_LWU,
285     MIPS_MEMOP_LD,
286     MIPS_MEMOP_SB,
287     MIPS_MEMOP_SH,
288     MIPS_MEMOP_SW,
289     MIPS_MEMOP_SD,
290    
291     MIPS_MEMOP_LWL,
292     MIPS_MEMOP_LWR,
293     MIPS_MEMOP_LDL,
294     MIPS_MEMOP_LDR,
295     MIPS_MEMOP_SWL,
296     MIPS_MEMOP_SWR,
297     MIPS_MEMOP_SDL,
298     MIPS_MEMOP_SDR,
299    
300     MIPS_MEMOP_LL,
301     MIPS_MEMOP_SC,
302    
303     MIPS_MEMOP_LDC1,
304     MIPS_MEMOP_SDC1,
305    
306     MIPS_MEMOP_CACHE,
307    
308     MIPS_MEMOP_MAX,
309     };
310    
311     /* 6 bits are reserved for device ID (see the memory subsystem) */
312     #define MIPS64_DEVICE_MAX (1 << 6)
313    
314     /* Number of recorded memory accesses (power of two) */
315     #define MEMLOG_COUNT 16
316    
317     /* Maximum number of breakpoints */
318     #define MIPS64_MAX_BREAKPOINTS 8
319    
320     typedef struct memlog_access memlog_access_t;
321     struct memlog_access {
322     m_uint64_t pc;
323     m_uint64_t vaddr;
324     m_uint64_t data;
325     m_uint32_t data_valid;
326     m_uint32_t op_size;
327     m_uint32_t op_type;
328     };
329    
330     /* MIPS CPU type */
331     typedef struct cpu_mips cpu_mips_t;
332    
333     /* Memory operation function prototype */
334     typedef fastcall u_int (*mips_memop_fn)(cpu_mips_t *cpu,m_uint64_t vaddr,
335     u_int reg);
336    
337     /* TLB entry definition */
338     typedef struct {
339     m_uint64_t mask;
340     m_uint64_t hi;
341     m_uint64_t lo0;
342     m_uint64_t lo1;
343     }tlb_entry_t;
344    
345     /* System Coprocessor (CP0) definition */
346     typedef struct {
347     m_uint64_t reg[MIPS64_CP0_REG_NR];
348     tlb_entry_t tlb[MIPS64_TLB_MAX_ENTRIES];
349    
350     /* Number of TLB entries */
351     u_int tlb_entries;
352    
353     /* Extensions for R7000 CP0 Set1 */
354     m_uint32_t ipl_lo,ipl_hi,int_ctl;
355     m_uint32_t derraddr0,derraddr1;
356     }mips_cp0_t;
357    
358     /* FPU Coprocessor (CP1) definition */
359     typedef struct {
360     m_uint64_t reg[MIPS64_CP1_REG_NR];
361     }mips_cp1_t;
362    
363     /* MTS64 entry */
364     typedef struct mts64_entry mts64_entry_t;
365     struct mts64_entry {
366     m_uint64_t start;
367     m_iptr_t action;
368     m_uint32_t mask;
369     m_uint32_t phys_page;
370     mts64_entry_t **pself;
371     mts64_entry_t *next,**pprev;
372     };
373    
374     /* MTS64 chunk forward declaration */
375     typedef struct mts64_chunk mts64_chunk_t;
376    
377     /* MIPS CPU definition */
378     struct cpu_mips {
379     /* MTS 1st level array */
380     void *mts_l1_ptr;
381    
382     /* MTS64 cache */
383     mts64_entry_t **mts64_cache;
384    
385     /* Virtual version of CP0 Compare Register */
386     m_uint32_t cp0_virt_cnt_reg,cp0_virt_cmp_reg;
387    
388     /* General Purpose Registers, Pointer Counter, LO/HI, IRQ */
389     m_uint32_t irq_pending,irq_cause,ll_bit;
390     m_uint64_t pc,gpr[MIPS64_GPR_NR];
391     m_uint64_t lo,hi,ret_pc;
392    
393     /* Code page translation cache */
394     insn_block_t **exec_phys_map;
395    
396     /* Virtual address to physical page translation */
397     fastcall int (*translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
398     m_uint32_t *phys_page);
399    
400     /* Memory access functions */
401     mips_memop_fn mem_op_fn[MIPS_MEMOP_MAX];
402    
403     /* Memory lookup function (to load ELF image,...) */
404     void *(*mem_op_lookup)(cpu_mips_t *cpu,m_uint64_t vaddr);
405    
406     /* System coprocessor (CP0) */
407     mips_cp0_t cp0;
408    
409     /* FPU (CP1) */
410     mips_cp1_t fpu;
411    
412     /* MTS32 array free list */
413     void *mts32_l2_free_list;
414    
415     /* Address bus mask */
416     m_uint64_t addr_bus_mask;
417    
418     /* IRQ counters and cause */
419     m_uint64_t irq_count,timer_irq_count,irq_fp_count;
420     pthread_mutex_t irq_lock;
421    
422     /* Current and free lists of instruction blocks */
423     insn_block_t *insn_block_list,*insn_block_last;
424     insn_block_t *insn_block_free_list;
425    
426     /* Executable page area */
427     void *exec_page_area;
428     size_t exec_page_area_size;
429     size_t exec_page_count,exec_page_alloc;
430     insn_exec_page_t *exec_page_free_list;
431     insn_exec_page_t *exec_page_array;
432    
433     /* "Idle" loop management */
434     volatile m_uint64_t idle_pc;
435     u_int idle_max,idle_sleep_time;
436     pthread_mutex_t idle_mutex;
437     pthread_cond_t idle_cond;
438    
439     /* IRQ disable flag */
440     volatile u_int irq_disable;
441    
442     /* Timer IRQs */
443     volatile u_int timer_irq_pending;
444     u_int timer_irq_freq;
445     u_int timer_irq_check_itv;
446     u_int timer_drift;
447    
448     /* IRQ idling preemption */
449     u_int irq_idle_preempt[8];
450    
451     /* CPU identifier for MP systems */
452     u_int id;
453    
454     /* CPU states */
455     volatile u_int state,prev_state;
456     volatile m_uint64_t seq_state;
457    
458     /* Thread running this CPU */
459     pthread_t cpu_thread;
460     int cpu_thread_running;
461    
462     /* VM instance */
463     vm_instance_t *vm;
464    
465     /* non-JIT mode instruction counter */
466     m_uint64_t insn_exec_count;
467    
468     /* MTS map/unmap/rebuild operations */
469     void (*mts_map)(cpu_mips_t *cpu,m_uint64_t vaddr,
470     m_uint64_t paddr,m_uint32_t len,
471     int cache_access,int tlb_index);
472    
473     void (*mts_unmap)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t len,
474     m_uint32_t val,int tlb_index);
475    
476     void (*mts_rebuild)(cpu_mips_t *cpu);
477    
478     /* MTS64 chunk list */
479     mts64_chunk_t *mts64_chunk_list;
480     mts64_chunk_t *mts64_chunk_free_list;
481     mts64_entry_t *mts64_entry_free_list;
482    
483     /* MTS64 cache statistics */
484     m_uint64_t mts64_misses,mts64_lookups;
485    
486     /* Reverse map for MTS64 */
487     mts64_entry_t *mts64_rmap[MIPS64_TLB_MAX_ENTRIES];
488    
489     /* JIT flush method */
490     u_int jit_flush_method;
491    
492     /* Number of compiled pages */
493     u_int compiled_pages;
494    
495     /* Fast memory operations use */
496     u_int fast_memop;
497    
498     /* Current exec page (non-JIT) info */
499     m_uint64_t njm_exec_page;
500     mips_insn_t *njm_exec_ptr;
501    
502     /* Performance counter (number of instructions executed by CPU) */
503     m_uint64_t perf_counter;
504    
505     /* Memory access log for fault debugging */
506     u_int memlog_pos;
507     memlog_access_t memlog_array[MEMLOG_COUNT];
508    
509     /* Breakpoints */
510     m_uint64_t breakpoints[MIPS64_MAX_BREAKPOINTS];
511     u_int breakpoints_enabled;
512    
513     /* Symtrace */
514     int sym_trace;
515     rbtree_tree *sym_tree;
516    
517     /* Next CPU in group */
518     cpu_mips_t *next;
519     };
520    
521     #define MIPS64_IRQ_LOCK(cpu) pthread_mutex_lock(&(cpu)->irq_lock)
522     #define MIPS64_IRQ_UNLOCK(cpu) pthread_mutex_unlock(&(cpu)->irq_lock)
523    
524     /* Register names */
525     extern char *mips64_gpr_reg_names[];
526    
527     /* Get cacheability info */
528     int mips64_cca_cached(m_uint8_t val);
529    
530     /* Reset a MIPS64 CPU */
531     int mips64_reset(cpu_mips_t *cpu);
532    
533     /* Initialize a MIPS64 processor */
534     int mips64_init(cpu_mips_t *cpu);
535    
536     /* Delete a MIPS64 processor */
537     void mips64_delete(cpu_mips_t *cpu);
538    
539     /* Set the CPU PRID register */
540     void mips64_set_prid(cpu_mips_t *cpu,m_uint32_t prid);
541    
542     /* Virtual idle loop */
543     void mips64_idle_loop(cpu_mips_t *cpu);
544    
545     /* Break idle wait state */
546     void mips64_idle_break_wait(cpu_mips_t *cpu);
547    
548     /* Timer IRQ */
549     void *mips64_timer_irq_run(cpu_mips_t *cpu);
550    
551     /* Determine an "idling" PC */
552     int mips64_get_idling_pc(cpu_mips_t *cpu);
553    
554     /* Update the IRQ flag */
555     void mips64_update_irq_flag(cpu_mips_t *cpu);
556    
557     /* Generate an exception */
558     void mips64_trigger_exception(cpu_mips_t *cpu,u_int exc_code,int bd_slot);
559    
560     /*
561     * Increment count register and trigger the timer IRQ if value in compare
562     * register is the same.
563     */
564     fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu);
565    
566     /* Trigger the Timer IRQ */
567     fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu);
568    
569     /* Execute ERET instruction */
570     fastcall void mips64_exec_eret(cpu_mips_t *cpu);
571    
572     /* Execute SYSCALL instruction */
573     fastcall void mips64_exec_syscall(cpu_mips_t *cpu);
574    
575     /* Execute BREAK instruction */
576     fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code);
577    
578     /* Trigger a Trap Exception */
579     fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu);
580    
581     /* Trigger IRQs */
582     fastcall void mips64_trigger_irq(cpu_mips_t *cpu);
583    
584     /* Set an IRQ */
585     void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq);
586    
587     /* Clear an IRQ */
588     void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq);
589    
590     /* DMFC1 */
591     fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
592    
593     /* DMTC1 */
594     fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
595    
596     /* MFC1 */
597     fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
598    
599     /* MTC1 */
600     fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
601    
602     /* Virtual breakpoint */
603     fastcall void mips64_run_breakpoint(cpu_mips_t *cpu);
604    
605     /* Debugging for register-jump to address 0 */
606     fastcall void mips64_debug_jr0(cpu_mips_t *cpu);
607    
608     /* Dump registers of a MIPS64 processor */
609     void mips64_dump_regs(cpu_mips_t *cpu);
610    
611     /* Dump a memory block */
612     void mips64_dump_memory(cpu_mips_t *cpu,m_uint64_t vaddr,u_int count);
613    
614     /* Dump the stack */
615     void mips64_dump_stack(cpu_mips_t *cpu,u_int count);
616    
617     /* Save the CPU state into a file */
618     int mips64_save_state(cpu_mips_t *cpu,char *filename);
619    
620     /* Load a raw image into the simulated memory */
621     int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr);
622    
623     /* Load an ELF image into the simulated memory */
624     int mips64_load_elf_image(cpu_mips_t *cpu,char *filename,
625     m_uint32_t *entry_point);
626    
627     /* Symbol lookup */
628     struct symbol *mips64_sym_lookup(cpu_mips_t *cpu,m_uint64_t addr);
629    
630     /* Insert a new symbol */
631     struct symbol *mips64_sym_insert(cpu_mips_t *cpu,char *name,m_uint64_t addr);
632    
633     /* Create the symbol tree */
634     int mips64_sym_create_tree(cpu_mips_t *cpu);
635    
636     /* Load a symbol file */
637     int mips64_sym_load_file(cpu_mips_t *cpu,char *filename);
638    
639     #endif

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