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dpavlin |
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/* |
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* Cisco 3600 simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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* |
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* NS16552 DUART. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "ptask.h" |
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#include "mips64.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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/* Interrupt Enable Register (IER) */ |
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#define IER_ERXRDY 0x1 |
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#define IER_ETXRDY 0x2 |
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/* Interrupt Identification Register */ |
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#define IIR_NPENDING 0x01 /* 0: irq pending, 1: no irq pending */ |
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#define IIR_TXRDY 0x02 |
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#define IIR_RXRDY 0x04 |
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/* Line Status Register (LSR) */ |
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#define LSR_RXRDY 0x01 |
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#define LSR_TXRDY 0x20 |
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#define LSR_TXEMPTY 0x40 |
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/* UART channel */ |
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struct ns16552_channel { |
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u_int ier,output; |
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vtty_t *vtty; |
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}; |
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/* NS16552 structure */ |
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struct ns16552_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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vm_instance_t *vm; |
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u_int irq; |
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dpavlin |
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/* Register offset divisor */ |
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u_int reg_div; |
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dpavlin |
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/* Periodic task to trigger DUART IRQ */ |
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ptask_id_t tid; |
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struct ns16552_channel channel[2]; |
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u_int duart_irq_seq; |
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}; |
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/* Console port input */ |
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static void tty_con_input(vtty_t *vtty) |
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{ |
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struct ns16552_data *d = vtty->priv_data; |
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if (d->channel[0].ier & IER_ERXRDY) |
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vm_set_irq(d->vm,d->irq); |
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} |
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/* AUX port input */ |
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static void tty_aux_input(vtty_t *vtty) |
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{ |
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struct ns16552_data *d = vtty->priv_data; |
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if (d->channel[1].ier & IER_ERXRDY) |
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vm_set_irq(d->vm,d->irq); |
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} |
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/* IRQ trickery for Console and AUX ports */ |
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static int tty_trigger_dummy_irq(struct ns16552_data *d,void *arg) |
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{ |
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d->duart_irq_seq++; |
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if (d->duart_irq_seq == 2) { |
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if (d->channel[0].ier & IER_ETXRDY) { |
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d->channel[0].output = TRUE; |
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vm_set_irq(d->vm,d->irq); |
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} |
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#if 0 |
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if (d->channel[1].ier & IER_ETXRDY) { |
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d->channel[1].output = TRUE; |
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vm_set_irq(d->vm,d->irq); |
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} |
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#endif |
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d->duart_irq_seq = 0; |
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} |
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return(0); |
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} |
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/* |
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* dev_ns16552_access() |
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*/ |
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void *dev_ns16552_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset, |
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u_int op_size,u_int op_type,m_uint64_t *data) |
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{ |
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struct ns16552_data *d = dev->priv_data; |
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int channel = 0; |
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u_char odata; |
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if (op_type == MTS_READ) |
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*data = 0; |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"NS16552","read from 0x%x, pc=0x%llx, ra=0x%llx\n", |
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offset,cpu->pc,cpu->gpr[MIPS_GPR_RA]); |
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} else { |
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cpu_log(cpu,"NS16552","write to 0x%x, value=0x%llx, pc=0x%llx\n", |
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offset,*data,cpu->pc); |
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} |
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#endif |
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dpavlin |
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offset >>= d->reg_div; |
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if (offset >= 0x08) |
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dpavlin |
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channel = 1; |
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switch(offset) { |
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/* Receiver Buffer Reg. (RBR) / Transmitting Holding Reg. (THR) */ |
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case 0x00: |
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dpavlin |
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case 0x08: |
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dpavlin |
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if (op_type == MTS_WRITE) { |
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vtty_put_char(d->channel[channel].vtty,(char)*data); |
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if (d->channel[channel].ier & IER_ETXRDY) |
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vm_set_irq(d->vm,d->irq); |
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d->channel[channel].output = TRUE; |
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} else { |
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*data = vtty_get_char(d->channel[channel].vtty); |
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} |
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break; |
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/* Interrupt Enable Register (IER) */ |
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dpavlin |
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case 0x01: |
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case 0x09: |
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dpavlin |
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if (op_type == MTS_READ) { |
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*data = d->channel[channel].ier; |
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} else { |
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d->channel[channel].ier = *data & 0xFF; |
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if ((*data & 0x02) == 0) { /* transmit holding register */ |
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d->channel[channel].vtty->managed_flush = TRUE; |
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vtty_flush(d->channel[channel].vtty); |
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} |
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} |
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break; |
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/* Interrupt Ident Register (IIR) */ |
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dpavlin |
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case 0x02: |
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dpavlin |
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vm_clear_irq(d->vm,d->irq); |
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dpavlin |
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case 0x0A: |
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dpavlin |
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if (op_type == MTS_READ) { |
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odata = IIR_NPENDING; |
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if (vtty_is_char_avail(d->channel[channel].vtty)) { |
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odata = IIR_RXRDY; |
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} else { |
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if (d->channel[channel].output) { |
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odata = IIR_TXRDY; |
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d->channel[channel].output = 0; |
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} |
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} |
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*data = odata; |
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} |
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break; |
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/* Line Status Register (LSR) */ |
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dpavlin |
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case 0x05: |
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case 0x0D: |
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dpavlin |
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if (op_type == MTS_READ) { |
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odata = 0; |
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if (vtty_is_char_avail(d->channel[channel].vtty)) |
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odata |= LSR_RXRDY; |
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odata |= LSR_TXRDY|LSR_TXEMPTY; |
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*data = odata; |
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} |
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break; |
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#if DEBUG_UNKNOWN |
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default: |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"NS16552","read from addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
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} else { |
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cpu_log(cpu,"NS16552","write to addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
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} |
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#endif |
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} |
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return NULL; |
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} |
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/* Shutdown a NS16552 device */ |
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void dev_ns16552_shutdown(vm_instance_t *vm,struct ns16552_data *d) |
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{ |
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if (d != NULL) { |
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d->channel[0].vtty->read_notifier = NULL; |
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d->channel[1].vtty->read_notifier = NULL; |
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/* Remove the periodic task */ |
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ptask_remove(d->tid); |
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/* Remove the device */ |
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dev_remove(vm,&d->dev); |
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/* Free the structure itself */ |
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free(d); |
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} |
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} |
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/* Create a NS16552 device */ |
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int dev_ns16552_init(vm_instance_t *vm,m_uint64_t paddr,m_uint32_t len, |
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dpavlin |
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u_int reg_div,u_int irq,vtty_t *vtty_A,vtty_t *vtty_B) |
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dpavlin |
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{ |
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struct ns16552_data *d; |
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/* Allocate private data structure */ |
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if (!(d = malloc(sizeof(*d)))) { |
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fprintf(stderr,"NS16552: out of memory\n"); |
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return(-1); |
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} |
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memset(d,0,sizeof(*d)); |
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d->vm = vm; |
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d->irq = irq; |
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dpavlin |
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d->reg_div = reg_div; |
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d->channel[0].vtty = vtty_A; |
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d->channel[1].vtty = vtty_B; |
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dpavlin |
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vm_object_init(&d->vm_obj); |
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d->vm_obj.name = "ns16552"; |
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d->vm_obj.data = d; |
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d->vm_obj.shutdown = (vm_shutdown_t)dev_ns16552_shutdown; |
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/* Set device properties */ |
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dev_init(&d->dev); |
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d->dev.name = "ns16552"; |
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d->dev.phys_addr = paddr; |
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d->dev.phys_len = len; |
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d->dev.handler = dev_ns16552_access; |
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d->dev.priv_data = d; |
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dpavlin |
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vtty_A->priv_data = d; |
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vtty_B->priv_data = d; |
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vtty_A->read_notifier = tty_con_input; |
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vtty_B->read_notifier = tty_aux_input; |
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dpavlin |
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/* Trigger periodically a dummy IRQ to flush buffers */ |
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d->tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,d,NULL); |
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/* Map this device to the VM */ |
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vm_bind_device(vm,&d->dev); |
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vm_object_add(vm,&d->vm_obj); |
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return(0); |
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} |