/[dynamips]/upstream/dynamips-0.2.6-RC2/dev_pa_a1.c
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Revision 3 - (show annotations)
Sat Oct 6 16:05:34 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 53918 byte(s)
dynamips-0.2.6-RC2

1 /*
2 * Cisco C7200 (Predator) Simulation Platform.
3 * Copyright (C) 2005,2006 Christophe Fillot. All rights reserved.
4 *
5 * PA-A1 ATM interface based on TI1570 and PLX 9060-ES.
6 *
7 * EEPROM types:
8 * - 0x17: PA-A1-OC3MM
9 * - 0x2C: PA-A1-OC3SM
10 * - 0x2D: PA-A1-OC3UTP
11 *
12 * IOS command: "sh controller atm2/0"
13 *
14 * Manuals:
15 *
16 * Texas Instruments TNETA1570 ATM segmentation and reassembly device
17 * with integrated 64-bit PCI-host interface
18 * http://focus.ti.com/docs/prod/folders/print/tneta1570.html
19 *
20 * PLX 9060-ES
21 * http://www.plxtech.com/products/io_accelerators/PCI9060/default.htm
22 *
23 * TODO:
24 * - RX error handling and RX AAL5-related stuff
25 * - HEC and AAL5 CRC fields.
26 *
27 * Cell trains for faster NETIO communications ?
28 */
29
30 #include <stdio.h>
31 #include <stdlib.h>
32 #include <string.h>
33 #include <unistd.h>
34 #include <errno.h>
35
36 #include "crc.h"
37 #include "atm.h"
38 #include "mips64.h"
39 #include "dynamips.h"
40 #include "memory.h"
41 #include "device.h"
42 #include "ptask.h"
43 #include "dev_c7200.h"
44
45 /* Debugging flags */
46 #define DEBUG_ACCESS 0
47 #define DEBUG_UNKNOWN 0
48 #define DEBUG_TRANSMIT 0
49 #define DEBUG_RECEIVE 0
50 #define DEBUG_TX_DMA 0
51
52 /* PCI vendor/product codes */
53 #define TI1570_PCI_VENDOR_ID 0x104c
54 #define TI1570_PCI_PRODUCT_ID 0xa001
55
56 #define PLX_9060ES_PCI_VENDOR_ID 0x10b5
57 #define PLX_9060ES_PCI_PRODUCT_ID 0x906e
58
59 /* Number of buffers transmitted at each TX DMA ring scan pass */
60 #define TI1570_TXDMA_PASS_COUNT 16
61
62 /* TI1570 Internal Registers (p.58 of doc) */
63 #define TI1570_REG_CONFIG 0x0000 /* Configuration registers */
64 #define TI1570_REG_STATUS 0x0001 /* Status register */
65 #define TI1570_REG_IMASK 0x0002 /* Interrupt-mask register */
66 #define TI1570_REG_RGT_RAT 0x0003 /* RGT + RAT cycle-counter */
67 #define TI1570_REG_RX_UNKNOWN 0x0004 /* RX Unknown Register */
68 #define TI1570_REG_TX_CRING_SIZE 0x0005 /* TX Completion ring sizes */
69 #define TI1570_REG_RX_CRING_SIZE 0x0006 /* RX Completion ring sizes */
70 #define TI1570_REG_TX_PSR_SIZE 0x0007 /* TX Pkt-seg ring size + FIFO */
71 #define TI1570_REG_HEC_AAL5_DISC 0x0008 /* HEC err + AAL5 CPCS discard */
72 #define TI1570_REG_UNK_PROTO_CNT 0x0009 /* Unknown-protocols counter */
73 #define TI1570_REG_RX_ATM_COUNT 0x000A /* ATM-cells-received counter */
74 #define TI1570_REG_TX_ATM_COUNT 0x000B /* ATM-cells-tranmitted counter */
75 #define TI1570_REG_TX_RX_FIFO 0x000C /* TX/RX FIFO occupancy, VCI mask */
76 #define TI1570_REG_SCHED_SIZE 0x000D /* Scheduler Table size */
77 #define TI1570_REG_SOFT_RESET 0x000E /* Software Reset */
78 #define TI1570_REG_TCR_WOI_ADDR 0x0080 /* TX Compl. Ring w/o IRQ addr. */
79 #define TI1570_REG_TCR_WI_ADDR 0x0081 /* TX Compl. Ring w/ IRQ addr. */
80 #define TI1570_REG_RCR_WOI_ADDR 0x0082 /* RX Compl. Ring w/o IRQ addr. */
81 #define TI1570_REG_RCR_WI_ADDR 0x0083 /* RX Compl. Ring w/ IRQ addr. */
82
83 /* TI1570 configuration register (p.59) */
84 #define TI1570_CFG_EN_RAT 0x00000001 /* Reassembly Aging */
85 #define TI1570_CFG_BP_SEL 0x00000002 /* IRQ on packet or buffer */
86 #define TI1570_CFG_EN_RX 0x00000010 /* RX enable */
87 #define TI1570_CFG_EN_TX 0x00000020 /* TX enable */
88 #define TI1570_CFG_SMALL_MAP 0x00000040 /* Small map */
89
90 /* TI1570 status register (p.61) */
91 #define TI1570_STAT_CP_TX 0x00000001 /* Transmit completion ring */
92 #define TI1570_STAT_RX_IRR 0x00000040 /* Receive unknown reg set */
93 #define TI1570_STAT_CP_RX 0x00000080 /* Receive completion ring */
94 #define TI1570_STAT_TX_FRZ 0x00000100 /* TX Freeze */
95 #define TI1570_STAT_RX_FRZ 0x00000200 /* RX Freeze */
96
97 /* Mask for RX/TX completion-ring sizes */
98 #define TI1570_TCR_SIZE_MASK 0x00001FFF /* TX compl. ring size mask */
99 #define TI1570_RCR_SIZE_MASK 0x000003FF /* RX compl. ring size mask */
100
101 /* TI1750 TX packet segmentation ring register */
102 #define TI1570_PSR_SIZE_MASK 0x000000FF /* pkt-seg ring size */
103
104 /* Total size of the TI1570 Control Memory */
105 #define TI1570_CTRL_MEM_SIZE 0x100000
106
107 /* Offsets of the TI1570 structures (p.66) */
108 #define TI1570_TX_SCHED_OFFSET 0x0000 /* TX scheduler table */
109 #define TI1570_INTERNAL_REGS_OFFSET 0x3200 /* Internal Registers */
110 #define TI1570_FREE_BUFFERS_OFFSET 0x3800 /* Free-Buffer Pointers */
111 #define TI1570_RX_DMA_PTR_TABLE_OFFSET 0x4000 /* RX VPI/VCI pointer table */
112 #define TI1570_TX_DMA_TABLE_OFFSET 0x8000 /* TX DMA state table */
113 #define TI1570_RX_DMA_TABLE_OFFSET 0x10000 /* RX DMA state table */
114
115 /* TX scheduler table */
116 #define TI1570_TX_SCHED_ENTRY_COUNT 6200
117 #define TI1570_TX_SCHED_ENTRY_MASK 0x3FF /* Entry mask */
118 #define TI1570_TX_SCHED_E0_SHIFT 0 /* Shift for entry 0 */
119 #define TI1570_TX_SCHED_E1_SHIFT 16 /* Shift for entry 0 */
120
121 /* TX DMA state table */
122 #define TI1570_TX_DMA_ACT 0x80000000 /* ACTive (word 0) */
123 #define TI1570_TX_DMA_SOP 0x40000000 /* Start of Packet (SOP) */
124 #define TI1570_TX_DMA_EOP 0x20000000 /* End of Packet (EOP) */
125 #define TI1570_TX_DMA_ABORT 0x10000000 /* Abort */
126 #define TI1570_TX_DMA_TCR_SELECT 0x02000000 /* TX comp. ring selection */
127 #define TI1570_TX_DMA_AAL_TYPE_MASK 0x0C000000 /* AAL-type mask */
128
129 #define TI1570_TX_DMA_AAL_TRWPTI 0x00000000 /* Transp. AAL w/ PTI set */
130 #define TI1570_TX_DMA_AAL_AAL5 0x04000000 /* AAL5 */
131 #define TI1570_TX_DMA_AAL_TRWOPTI 0x08000000 /* Transp. AAL w/o PTI set */
132
133 #define TI1570_TX_DMA_OFFSET_MASK 0x00FF0000
134 #define TI1570_TX_DMA_OFFSET_SHIFT 16
135 #define TI1570_TX_DMA_DCOUNT_MASK 0x0000FFFF
136
137 #define TI1570_TX_DMA_ON 0x80000000 /* DMA state (word 3) */
138 #define TI1570_TX_DMA_RING_OFFSET_MASK 0x3FFFFF00
139 #define TI1570_TX_DMA_RING_OFFSET_SHIFT 8
140 #define TI1570_TX_DMA_RING_INDEX_MASK 0x000000FF
141
142 #define TI1570_TX_DMA_RING_AAL5_LEN_MASK 0x0000FFFF
143
144 typedef struct ti1570_tx_dma_entry ti1570_tx_dma_entry_t;
145 struct ti1570_tx_dma_entry {
146 m_uint32_t ctrl_buf; /* Ctrl, Buffer Offset, Buffer data-byte count */
147 m_uint32_t cb_addr; /* Current Buffer Address */
148 m_uint32_t atm_hdr; /* 4-byte ATM header */
149 m_uint32_t dma_state; /* DMA state + Packet segmentation ring address */
150 m_uint32_t nb_addr; /* Next Buffer address */
151 m_uint32_t sb_addr; /* Start of Buffer address */
152 m_uint32_t aal5_crc; /* Partial AAL5-transmit CRC */
153 m_uint32_t aal5_ctrl; /* AAL5-control field and length field */
154 };
155
156 /* TX Packet-Segmentation Rings */
157 #define TI1570_TX_RING_OWN 0x80000000 /* If set, packet is ready */
158 #define TI1570_TX_RING_PTR_MASK 0x3FFFFFFF /* Buffer pointer */
159
160 /* TX Data Buffers */
161 #define TI1570_TX_BUFFER_RDY 0x80000000 /* If set, buffer is ready */
162 #define TI1570_TX_BUFFER_SOP 0x40000000 /* First buffer of packet */
163 #define TI1570_TX_BUFFER_EOP 0x20000000 /* Last buffer of packet */
164 #define TI1570_TX_BUFFER_ABORT 0x10000000 /* Abort */
165
166 #define TI1570_TX_BUFFER_OFFSET_MASK 0x00FF0000
167 #define TI1570_TX_BUFFER_OFFSET_SHIFT 16
168 #define TI1570_TX_BUFFER_DCOUNT_MASK 0x0000FFFF
169
170 typedef struct ti1570_tx_buffer ti1570_tx_buffer_t;
171 struct ti1570_tx_buffer {
172 m_uint32_t ctrl_buf; /* Ctrl, Buffer offset, Buffer data-byte count */
173 m_uint32_t nb_addr; /* Start-of-next buffer pointer */
174 m_uint32_t atm_hdr; /* 4-byte ATM header */
175 m_uint32_t aal5_ctrl; /* PCS-UU/CPI field (AAL5 control field) */
176 };
177
178 /* TX completion-ring */
179 #define TI1570_TCR_OWN 0x80000000 /* OWNner bit */
180 #define TI1570_TCR_ABORT 0x40000000 /* Abort */
181
182 /* RX VPI/VCI DMA pointer table */
183 #define TI1570_RX_VPI_ENABLE 0x80000000 /* VPI enabled ? */
184 #define TI1570_RX_BASE_PTR_MASK 0x7FFF0000 /* Base pointer mask */
185 #define TI1570_RX_BASE_PTR_SHIFT 16 /* Base pointer shift */
186 #define TI1570_RX_VCI_RANGE_MASK 0x0000FFFF /* Valid VCI range */
187
188 /* RX DMA state table (p.36) */
189 #define TI1570_RX_DMA_ACT 0x80000000 /* ACTive (word 0) */
190 #define TI1570_RX_DMA_RCR_SELECT 0x20000000 /* RX comp. ring selection */
191 #define TI1570_RX_DMA_WAIT_EOP 0x10000000 /* Wait for EOP */
192 #define TI1570_RX_DMA_AAL_TYPE_MASK 0x0C000000 /* AAL-type mask */
193
194 #define TI1570_RX_DMA_AAL_PTI 0x00000000 /* PTI based tr. AAL pkt */
195 #define TI1570_RX_DMA_AAL_AAL5 0x04000000 /* AAL5 */
196 #define TI1570_RX_DMA_AAL_CNT 0x08000000 /* Cnt based tr. AAL pkt */
197
198 #define TI1570_RX_DMA_FIFO 0x02000000 /* FIFO used for free bufs */
199
200 #define TI1570_RX_DMA_TR_CNT_MASK 0xFFFF0000 /* Cnt-based Tr-AAL */
201 #define TI1570_RX_DMA_TR_CNT_SHIFT 16
202 #define TI1570_RX_DMA_CB_LEN_MASK 0x0000FFFF /* Current buffer length */
203
204 #define TI1570_RX_DMA_ON 0x80000000 /* DMA state (word 6) */
205 #define TI1570_RX_DMA_FILTER 0x40000000 /* Filter */
206
207 #define TI1570_RX_DMA_FB_PTR_MASK 0x3FFFFFFF /* Free-buffer ptr mask */
208 #define TI1570_RX_DMA_FB_INDEX_MASK 0x000000FF /* Index with Free-buf ring */
209
210 typedef struct ti1570_rx_dma_entry ti1570_rx_dma_entry_t;
211 struct ti1570_rx_dma_entry {
212 m_uint32_t ctrl; /* Control field, EFCN cell cnt, pkt length */
213 m_uint32_t cb_addr; /* Current Buffer Address */
214 m_uint32_t sb_addr; /* Start of Buffer address */
215 m_uint32_t cb_len; /* Transp-AAL pkt counter, current buf length */
216 m_uint32_t sp_ptr; /* Start-of-packet pointer */
217 m_uint32_t aal5_crc; /* Partial AAL5-receive CRC */
218 m_uint32_t fbr_entry; /* Free-buffer ring-pointer table entry */
219 m_uint32_t timeout; /* Timeout value, current timeout count */
220 };
221
222 /* RX free-buffer ring pointer table entry (p.39) */
223 #define TI1570_RX_FBR_PTR_MASK 0xFFFFFFFC
224 #define TI1570_RX_FBR_BS_MASK 0xFFFF0000 /* Buffer size mask */
225 #define TI1570_RX_FBR_BS_SHIFT 16
226 #define TI1570_RX_FBR_RS_MASK 0x0000FC00 /* Ring size mask */
227 #define TI1570_RX_FBR_RS_SHIFT 10
228 #define TI1570_RX_FBR_IDX_MASK 0x000003FF /* Current index mask */
229
230 typedef struct ti1570_rx_fbr_entry ti1570_rx_fbr_entry_t;
231 struct ti1570_rx_fbr_entry {
232 m_uint32_t fbr_ptr; /* RX free-buffer ring pointer */
233 m_uint32_t ring_size; /* Ring size and buffer size */
234 };
235
236 /* RX buffer pointer (p.41) */
237 #define TI1570_RX_BUFPTR_OWN 0x80000000 /* If set, buffer is ready */
238 #define TI1570_RX_BUFPTR_MASK 0x3FFFFFFF /* Buffer address mask */
239
240 /* RX data buffer (p.42) */
241 #define TI1570_RX_BUFFER_SOP 0x80000000 /* Start-of-Packet buffer */
242 #define TI1570_RX_BUFFER_EOP 0x40000000 /* End-of-Packet buffer */
243
244 typedef struct ti1570_rx_buffer ti1570_rx_buffer_t;
245 struct ti1570_rx_buffer {
246 m_uint32_t reserved; /* Reserved, not used by the TI1570 */
247 m_uint32_t ctrl; /* Control field, Start of next buffer pointer */
248 m_uint32_t atm_hdr; /* ATM header */
249 m_uint32_t user; /* User-defined value */
250 };
251
252 /* Internal structure to hold free buffer info */
253 typedef struct ti1570_rx_buf_holder ti1570_rx_buf_holder_t;
254 struct ti1570_rx_buf_holder {
255 m_uint32_t buf_addr;
256 m_uint32_t buf_size;
257 ti1570_rx_buffer_t rx_buf;
258 };
259
260 /* RX completion ring entry */
261 #define TI1570_RCR_PKT_OVFLW 0x80000000 /* Packet overflow (word 0) */
262 #define TI1570_RCR_CRC_ERROR 0x40000000 /* CRC error */
263 #define TI1570_RCR_BUF_STARV 0x20000000 /* Buffer starvation */
264 #define TI1570_RCR_TIMEOUT 0x10000000 /* Reassembly timeout */
265 #define TI1570_RCR_ABORT 0x08000000 /* Abort condition */
266 #define TI1570_RCR_AAL5 0x04000000 /* AAL5 indicator */
267
268 #define TI1570_RCR_VALID 0x80000000 /* Start-ptr valid (word 2) */
269
270 #define TI1570_RCR_OWN 0x80000000 /* Buffer ready (word 4) */
271 #define TI1570_RCR_ERROR 0x40000000 /* Error entry */
272
273 typedef struct ti1570_rcr_entry ti1570_rcr_entry_t;
274 struct ti1570_rcr_entry {
275 m_uint32_t atm_hdr; /* ATM header */
276 m_uint32_t error; /* Error Indicator + Congestion cell count */
277 m_uint32_t sp_addr; /* Start of packet */
278 m_uint32_t aal5_trailer; /* AAL5 trailer */
279 m_uint32_t fbr_entry; /* Free-buffer ring-pointer table entry */
280 m_uint32_t res[3]; /* Reserved, not used by the TI1570 */
281 };
282
283 /* TI1570 Data */
284 struct pa_a1_data {
285 char *name;
286
287 /* Control Memory pointer */
288 m_uint32_t *ctrl_mem_ptr;
289
290 /* TI1570 internal registers */
291 m_uint32_t *iregs;
292
293 /* TX FIFO cell */
294 m_uint8_t txfifo_cell[ATM_CELL_SIZE];
295 m_uint32_t txfifo_avail,txfifo_pos;
296
297 /* TX Scheduler table */
298 m_uint32_t *tx_sched_table;
299
300 /* TX DMA state table */
301 ti1570_tx_dma_entry_t *tx_dma_table;
302
303 /* TX/RX completion ring current position */
304 m_uint32_t tcr_wi_pos,tcr_woi_pos;
305 m_uint32_t rcr_wi_pos,rcr_woi_pos;
306
307 /* RX VPI/VCI DMA pointer table */
308 m_uint32_t *rx_vpi_vci_dma_table;
309
310 /* RX DMA state table */
311 ti1570_rx_dma_entry_t *rx_dma_table;
312
313 /* RX Free-buffer ring pointer table */
314 ti1570_rx_fbr_entry_t *rx_fbr_table;
315
316 /* Virtual device */
317 struct vdevice *dev;
318
319 /* PCI device information */
320 struct pci_device *pci_dev_ti,*pci_dev_plx;
321
322 /* Virtual machine */
323 vm_instance_t *vm;
324
325 /* NetIO descriptor */
326 netio_desc_t *nio;
327
328 /* TX ring scanner task id */
329 ptask_id_t tx_tid;
330 };
331
332 /* Log a TI1570 message */
333 #define TI1570_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg)
334
335 /* Reset the TI1570 (forward declaration) */
336 static void ti1570_reset(struct pa_a1_data *d,int clear_ctrl_mem);
337
338 /*
339 * dev_pa_a1_access()
340 */
341 void *dev_pa_a1_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,
342 u_int op_size,u_int op_type,m_uint64_t *data)
343 {
344 struct pa_a1_data *d = dev->priv_data;
345
346 if (op_type == MTS_READ)
347 *data = 0;
348
349 #if DEBUG_ACCESS
350 if (op_type == MTS_READ) {
351 cpu_log(cpu,"TI1570","read access to offset = 0x%x, pc = 0x%llx\n",
352 offset,cpu->pc);
353 } else {
354 cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, "
355 "val = 0x%llx\n",offset,cpu->pc,*data);
356 }
357 #endif
358
359 /* Specific cases */
360 switch(offset) {
361 case 0x3238:
362 TI1570_LOG(d,"reset issued.\n");
363 ti1570_reset(d,FALSE);
364 break;
365
366 case 0x18000c:
367 if (op_type == MTS_READ) {
368 *data = 0xa6;
369 return NULL;
370 }
371 break;
372 }
373
374 /* Control Memory access */
375 if (offset < TI1570_CTRL_MEM_SIZE) {
376 if (op_type == MTS_READ)
377 *data = d->ctrl_mem_ptr[offset >> 2];
378 else
379 d->ctrl_mem_ptr[offset >> 2] = *data;
380 return NULL;
381 }
382
383 /* Unknown offset */
384 #if DEBUG_UNKNOWN
385 if (op_type == MTS_READ) {
386 cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
387 offset,cpu->pc,op_size);
388 } else {
389 cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, "
390 "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);
391 }
392 #endif
393 return NULL;
394 }
395
396 /* Fetch a TX data buffer from host memory */
397 static void ti1570_read_tx_buffer(struct pa_a1_data *d,m_uint32_t addr,
398 ti1570_tx_buffer_t *tx_buf)
399 {
400 physmem_copy_from_vm(d->vm,tx_buf,addr,sizeof(ti1570_tx_buffer_t));
401
402 /* byte-swapping */
403 tx_buf->ctrl_buf = vmtoh32(tx_buf->ctrl_buf);
404 tx_buf->nb_addr = vmtoh32(tx_buf->nb_addr);
405 tx_buf->atm_hdr = vmtoh32(tx_buf->atm_hdr);
406 tx_buf->aal5_ctrl = vmtoh32(tx_buf->aal5_ctrl);
407 }
408
409 /* Acquire a TX buffer */
410 static int ti1570_acquire_tx_buffer(struct pa_a1_data *d,
411 ti1570_tx_dma_entry_t *tde,
412 m_uint32_t buf_addr)
413 {
414 ti1570_tx_buffer_t tx_buf;
415 m_uint32_t buf_offset;
416
417 #if DEBUG_TRANSMIT
418 TI1570_LOG(d,"ti1570_acquire_tx_buffer: acquiring buffer at address 0x%x\n",
419 buf_addr);
420 #endif
421
422 /* Read the TX buffer from host memory */
423 ti1570_read_tx_buffer(d,buf_addr,&tx_buf);
424
425 /* The buffer must be ready to be acquired */
426 if (!(tx_buf.ctrl_buf & TI1570_TX_BUFFER_RDY))
427 return(FALSE);
428
429 /* Put the TX buffer data into the TX DMA state entry */
430 tde->ctrl_buf = tx_buf.ctrl_buf;
431 tde->nb_addr = tx_buf.nb_addr << 2;
432
433 /* Read the ATM header only from the first buffer */
434 if (tx_buf.ctrl_buf & TI1570_TX_BUFFER_SOP) {
435 tde->atm_hdr = tx_buf.atm_hdr;
436 tde->aal5_ctrl = tx_buf.aal5_ctrl;
437 tde->aal5_crc = 0xFFFFFFFF;
438 }
439
440 /* Compute the current-buffer-data address */
441 buf_offset = tx_buf.ctrl_buf & TI1570_TX_BUFFER_OFFSET_MASK;
442 buf_offset >>= TI1570_TX_BUFFER_OFFSET_SHIFT;
443 tde->cb_addr = buf_addr + sizeof(tx_buf) + buf_offset;
444
445 /* Remember the start address of the buffer */
446 tde->sb_addr = buf_addr;
447 return(TRUE);
448 }
449
450 /* Returns TRUE if the TX DMA entry is for an AAL5 packet */
451 static inline int ti1570_is_tde_aal5(ti1570_tx_dma_entry_t *tde)
452 {
453 m_uint32_t pkt_type;
454
455 pkt_type = tde->ctrl_buf & TI1570_TX_DMA_AAL_TYPE_MASK;
456 return(pkt_type == TI1570_TX_DMA_AAL_AAL5);
457 }
458
459 /* Update the AAL5 partial CRC */
460 static void ti1570_update_aal5_crc(struct pa_a1_data *d,
461 ti1570_tx_dma_entry_t *tde)
462 {
463 tde->aal5_crc = crc32_compute(tde->aal5_crc,
464 &d->txfifo_cell[ATM_HDR_SIZE],
465 ATM_PAYLOAD_SIZE);
466 }
467
468 /*
469 * Update the TX DMA entry buffer offset and count when "data_len" bytes
470 * have been transmitted.
471 */
472 static void ti1570_update_tx_dma_bufinfo(ti1570_tx_dma_entry_t *tde,
473 m_uint32_t buf_size,
474 m_uint32_t data_len)
475 {
476 m_uint32_t tmp,tot_len;
477
478 /* update the current buffer address */
479 tde->cb_addr += data_len;
480
481 /* set the remaining byte count */
482 tmp = tde->ctrl_buf & ~TI1570_TX_BUFFER_DCOUNT_MASK;
483 tde->ctrl_buf = tmp + (buf_size - data_len);
484
485 /* update the AAL5 count */
486 if (ti1570_is_tde_aal5(tde)) {
487 tot_len = tde->aal5_ctrl & TI1570_TX_DMA_RING_AAL5_LEN_MASK;
488 tot_len += data_len;
489
490 tmp = (tde->aal5_ctrl & ~TI1570_TX_DMA_RING_AAL5_LEN_MASK) + tot_len;
491 tde->aal5_ctrl = tmp;
492 }
493 }
494
495 /* Clear the TX fifo */
496 static void ti1570_clear_tx_fifo(struct pa_a1_data *d)
497 {
498 d->txfifo_avail = ATM_PAYLOAD_SIZE;
499 d->txfifo_pos = ATM_HDR_SIZE;
500 memset(d->txfifo_cell,0,ATM_CELL_SIZE);
501 }
502
503 /*
504 * Transmit the TX FIFO cell through the NETIO infrastructure if
505 * it is full.
506 */
507 static void ti1570_send_tx_fifo(struct pa_a1_data *d,
508 ti1570_tx_dma_entry_t *tde,
509 int update_aal5_crc)
510 {
511 if (d->txfifo_avail == 0) {
512 #if DEBUG_TRANSMIT
513 TI1570_LOG(d,"ti1570_transmit_cell: transmitting to NETIO device\n");
514 mem_dump(log_file,d->txfifo_cell,ATM_CELL_SIZE);
515 #endif
516 if (update_aal5_crc)
517 ti1570_update_aal5_crc(d,tde);
518
519 netio_send(d->nio,d->txfifo_cell,ATM_CELL_SIZE);
520 ti1570_clear_tx_fifo(d);
521 }
522 }
523
524 /* Add padding to the FIFO */
525 static void ti1570_add_tx_padding(struct pa_a1_data *d,m_uint32_t len)
526 {
527 if (len > d->txfifo_avail) {
528 TI1570_LOG(d,"ti1570_add_tx_padding: trying to add too large "
529 "padding (avail: 0x%x, pad: 0x%x)\n",d->txfifo_avail,len);
530 len = d->txfifo_avail;
531 }
532
533 memset(&d->txfifo_cell[d->txfifo_pos],0,len);
534 d->txfifo_pos += len;
535 d->txfifo_avail -= len;
536 }
537
538 /* Initialize an ATM cell for tranmitting */
539 static m_uint32_t ti1570_init_tx_atm_cell(struct pa_a1_data *d,
540 ti1570_tx_dma_entry_t *tde,
541 int set_pti)
542 {
543 m_uint32_t buf_size,len,atm_hdr;
544
545 buf_size = tde->ctrl_buf & TI1570_TX_DMA_DCOUNT_MASK;
546 len = m_min(buf_size,d->txfifo_avail);
547
548 #if DEBUG_TRANSMIT
549 TI1570_LOG(d,"ti1570_init_tx_atm_cell: data ptr=0x%x, "
550 "buf_size=%u (0x%x), len=%u (0x%x), atm_hdr=0x%x\n",
551 tde->cb_addr,buf_size,buf_size,len,len,tde->atm_hdr);
552 #endif
553
554 /* copy the ATM header */
555 atm_hdr = tde->atm_hdr;
556
557 if (set_pti) {
558 atm_hdr &= ~ATM_PTI_NETWORK;
559 atm_hdr |= ATM_PTI_EOP;
560 }
561
562 *(m_uint32_t *)d->txfifo_cell = htonl(atm_hdr);
563
564 /* compute HEC field */
565 atm_insert_hec(d->txfifo_cell);
566
567 /* copy the payload and try to transmit if the FIFO is full */
568 if (len > 0) {
569 physmem_copy_from_vm(d->vm,&d->txfifo_cell[d->txfifo_pos],
570 tde->cb_addr,len);
571 d->txfifo_pos += len;
572 d->txfifo_avail -= len;
573 }
574
575 ti1570_update_tx_dma_bufinfo(tde,buf_size,len);
576 return(len);
577 }
578
579 /*
580 * Transmit an Transparent-AAL ATM cell through the NETIO infrastructure.
581 */
582 static int ti1570_transmit_transp_cell(struct pa_a1_data *d,
583 ti1570_tx_dma_entry_t *tde,
584 int atm_set_eop,int *buf_end)
585 {
586 m_uint32_t buf_size,len;
587 int pkt_end,last_cell;
588
589 pkt_end = tde->ctrl_buf & TI1570_TX_DMA_EOP;
590 buf_size = tde->ctrl_buf & TI1570_TX_DMA_DCOUNT_MASK;
591 last_cell = FALSE;
592
593 if (!pkt_end) {
594 len = ti1570_init_tx_atm_cell(d,tde,FALSE);
595 ti1570_send_tx_fifo(d,tde,FALSE);
596
597 if ((buf_size - len) == 0)
598 *buf_end = TRUE;
599
600 return(FALSE);
601 }
602
603 /* this is the end of packet and the last buffer */
604 if (buf_size <= d->txfifo_avail)
605 last_cell = TRUE;
606
607 len = ti1570_init_tx_atm_cell(d,tde,last_cell & atm_set_eop);
608 if (last_cell) ti1570_add_tx_padding(d,d->txfifo_avail);
609 ti1570_send_tx_fifo(d,tde,FALSE);
610 return(last_cell);
611 }
612
613 /* Add the AAL5 trailer to the TX FIFO */
614 static void ti1570_add_aal5_trailer(struct pa_a1_data *d,
615 ti1570_tx_dma_entry_t *tde)
616 {
617 m_uint8_t *trailer;
618
619 trailer = &d->txfifo_cell[ATM_AAL5_TRAILER_POS];
620
621 /* Control field + Length */
622 *(m_uint32_t *)trailer = htonl(tde->aal5_ctrl);
623
624 /* Final CRC-32 computation */
625 tde->aal5_crc = crc32_compute(tde->aal5_crc,
626 &d->txfifo_cell[ATM_HDR_SIZE],
627 ATM_PAYLOAD_SIZE - 4);
628
629 *(m_uint32_t *)(trailer+4) = htonl(~tde->aal5_crc);
630
631 /* Consider the FIFO as full */
632 d->txfifo_avail = 0;
633 }
634
635 /*
636 * Tranmit an AAL5 cell through the NETIO infrastructure.
637 *
638 * Returns TRUE if this is the real end of packet.
639 */
640 static int ti1570_transmit_aal5_cell(struct pa_a1_data *d,
641 ti1570_tx_dma_entry_t *tde,
642 int *buf_end)
643 {
644 m_uint32_t buf_size,len;
645 int pkt_end;
646
647 pkt_end = tde->ctrl_buf & TI1570_TX_DMA_EOP;
648 buf_size = tde->ctrl_buf & TI1570_TX_DMA_DCOUNT_MASK;
649
650 #if DEBUG_TRANSMIT
651 TI1570_LOG(d,"ti1570_transmit_aal5_cell: data ptr=0x%x, "
652 "buf_size=0x%x (%u)\n",tde->cb_addr,buf_size,buf_size);
653 #endif
654
655 /* If this is not the end of packet, transmit the cell normally */
656 if (!pkt_end) {
657 len = ti1570_init_tx_atm_cell(d,tde,FALSE);
658 ti1570_send_tx_fifo(d,tde,TRUE);
659
660 if ((buf_size - len) == 0)
661 *buf_end = TRUE;
662
663 return(FALSE);
664 }
665
666 /*
667 * This is the end of packet, check if we need to emit a special cell
668 * for the AAL5 trailer.
669 */
670 if ((buf_size + ATM_AAL5_TRAILER_SIZE) <= d->txfifo_avail) {
671 len = ti1570_init_tx_atm_cell(d,tde,TRUE);
672
673 /* add the padding */
674 ti1570_add_tx_padding(d,d->txfifo_avail - ATM_AAL5_TRAILER_SIZE);
675
676 /* add the AAL5 trailer at offset 40 */
677 ti1570_add_aal5_trailer(d,tde);
678
679 /* we can transmit the cell */
680 ti1570_send_tx_fifo(d,tde,FALSE);
681
682 *buf_end = TRUE;
683 return(TRUE);
684 }
685
686 /* Transmit the cell normally */
687 len = ti1570_init_tx_atm_cell(d,tde,FALSE);
688 ti1570_add_tx_padding(d,d->txfifo_avail);
689 ti1570_send_tx_fifo(d,tde,TRUE);
690 return(FALSE);
691 }
692
693 /* Update the TX completion ring */
694 static void ti1570_update_tx_cring(struct pa_a1_data *d,
695 ti1570_tx_dma_entry_t *tde)
696 {
697 m_uint32_t tcr_addr,tcr_end,val;
698
699 if (tde->ctrl_buf & TI1570_TX_DMA_TCR_SELECT) {
700 /* TX completion ring with interrupt */
701 tcr_addr = d->iregs[TI1570_REG_TCR_WI_ADDR] + (d->tcr_wi_pos * 4);
702 } else {
703 /* TX completion ring without interrupt */
704 tcr_addr = d->iregs[TI1570_REG_TCR_WOI_ADDR] + (d->tcr_woi_pos * 4);
705 }
706
707 #if DEBUG_TRANSMIT
708 TI1570_LOG(d,"ti1570_update_tx_cring: posting 0x%x at address 0x%x\n",
709 tde->sb_addr,tcr_addr);
710
711 physmem_dump_vm(d->vm,tde->sb_addr,sizeof(ti1570_tx_buffer_t) >> 2);
712 #endif
713
714 /* we have a TX freeze if the buffer belongs to the host */
715 val = physmem_copy_u32_from_vm(d->vm,tcr_addr);
716 if (!(val & TI1570_TCR_OWN)) {
717 d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_TX_FRZ;
718 return;
719 }
720
721 /* put the buffer address in the ring */
722 val = tde->sb_addr >> 2;
723
724 if (tde->ctrl_buf & TI1570_TX_DMA_ABORT)
725 val |= TI1570_TCR_ABORT;
726
727 physmem_copy_u32_to_vm(d->vm,tcr_addr,val);
728
729 /* update the internal position pointer */
730 if (tde->ctrl_buf & TI1570_TX_DMA_TCR_SELECT) {
731 tcr_end = d->iregs[TI1570_REG_TX_CRING_SIZE] & TI1570_TCR_SIZE_MASK;
732
733 if ((d->tcr_wi_pos++) == tcr_end)
734 d->tcr_wi_pos = 0;
735 } else {
736 tcr_end = (d->iregs[TI1570_REG_TX_CRING_SIZE] >> 16);
737 tcr_end &= TI1570_TCR_SIZE_MASK;
738
739 if ((d->tcr_woi_pos++) == tcr_end)
740 d->tcr_woi_pos = 0;
741 }
742 }
743
744 /* Analyze a TX DMA state table entry */
745 static int ti1570_scan_tx_dma_entry_single(struct pa_a1_data *d,
746 m_uint32_t index)
747 {
748 ti1570_tx_dma_entry_t *tde;
749 m_uint32_t psr_base,psr_addr,psr_entry,psr_end;
750 m_uint32_t buf_addr,buf_size,pkt_type,tmp;
751 m_uint32_t psr_index;
752 int atm_set_eop = 0;
753 int pkt_end,buf_end = 0;
754
755 tde = &d->tx_dma_table[index];
756
757 /* The DMA channel state flag must be ON */
758 if (!(tde->dma_state & TI1570_TX_DMA_ON))
759 return(FALSE);
760
761 #if DEBUG_TX_DMA
762 /* We have a running DMA channel */
763 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: TX DMA entry %u is ON "
764 "(ctrl_buf = 0x%x)\n",index,tde->ctrl_buf);
765 #endif
766
767 /* Is this the start of a new packet ? */
768 if (!(tde->ctrl_buf & TI1570_TX_DMA_ACT))
769 {
770 #if DEBUG_TX_DMA
771 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: TX DMA entry %u is not ACT\n",
772 index);
773 #endif
774
775 /* No packet yet, fetch it from the packet-segmentation ring */
776 psr_base = tde->dma_state & TI1570_TX_DMA_RING_OFFSET_MASK;
777 psr_index = tde->dma_state & TI1570_TX_DMA_RING_INDEX_MASK;
778
779 /* Compute address of the current packet segmentation ring entry */
780 psr_addr = (psr_base + psr_index) << 2;
781 psr_entry = physmem_copy_u32_from_vm(d->vm,psr_addr);
782
783 #if DEBUG_TX_DMA
784 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: psr_addr = 0x%x, "
785 "psr_entry = 0x%x\n",psr_addr,psr_entry);
786 #endif
787
788 /* The packet-segmentation-ring entry is owned by host, quit now */
789 if (!(psr_entry & TI1570_TX_RING_OWN))
790 return(FALSE);
791
792 /* Acquire the first buffer (it MUST be in the ready state) */
793 buf_addr = (psr_entry & TI1570_TX_RING_PTR_MASK) << 2;
794
795 if (!ti1570_acquire_tx_buffer(d,tde,buf_addr)) {
796 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: PSR entry with OWN bit set "
797 "but buffer without RDY bit set.\n");
798 return(FALSE);
799 }
800
801 /* Set ACT bit for the DMA channel */
802 tde->ctrl_buf |= TI1570_TX_DMA_ACT;
803 }
804
805 /* Compute the remaining size and determine the packet type */
806 buf_size = tde->ctrl_buf & TI1570_TX_DMA_DCOUNT_MASK;
807 pkt_type = tde->ctrl_buf & TI1570_TX_DMA_AAL_TYPE_MASK;
808 pkt_end = tde->ctrl_buf & TI1570_TX_DMA_EOP;
809
810 #if DEBUG_TRANSMIT
811 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: ctrl_buf=0x%8.8x, "
812 "cb_addr=0x%8.8x, atm_hdr=0x%8.8x, dma_state=0x%8.8x\n",
813 tde->ctrl_buf, tde->cb_addr, tde->atm_hdr, tde->dma_state);
814
815 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: nb_addr=0x%8.8x, "
816 "sb_addr=0x%8.8x, aal5_crc=0x%8.8x, aal5_ctrl=0x%8.8x\n",
817 tde->nb_addr, tde->sb_addr, tde->aal5_crc, tde->aal5_ctrl);
818 #endif
819
820 /*
821 * If the current buffer is now empty and if this is not the last
822 * buffer in the current packet, try to fetch a new buffer.
823 * If the next buffer is not yet ready, we have finished.
824 */
825 if (!buf_size && !pkt_end && !ti1570_acquire_tx_buffer(d,tde,tde->nb_addr))
826 return(FALSE);
827
828 switch(pkt_type) {
829 case TI1570_TX_DMA_AAL_TRWPTI:
830 atm_set_eop = 1;
831
832 case TI1570_TX_DMA_AAL_TRWOPTI:
833 /* Transmit the ATM cell transparently */
834 pkt_end = ti1570_transmit_transp_cell(d,tde,atm_set_eop,&buf_end);
835 break;
836
837 case TI1570_TX_DMA_AAL_AAL5:
838 pkt_end = ti1570_transmit_aal5_cell(d,tde,&buf_end);
839 break;
840
841 default:
842 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: invalid AAL-type\n");
843 return(FALSE);
844 }
845
846 /* Re-read the remaining buffer size */
847 buf_size = tde->ctrl_buf & TI1570_TX_DMA_DCOUNT_MASK;
848
849 /* Put the buffer address in the transmit completion ring */
850 if (buf_end) ti1570_update_tx_cring(d,tde);
851
852 /*
853 * If we have reached end of packet (EOP): clear the ACT bit,
854 * give back the packet-segmentation ring entry to the host,
855 * and increment the PSR index.
856 */
857 if (pkt_end) {
858 tde->ctrl_buf &= ~TI1570_TX_DMA_ACT;
859
860 /* Clear the OWN bit of the packet-segmentation ring entry */
861 psr_base = tde->dma_state & TI1570_TX_DMA_RING_OFFSET_MASK;
862 psr_index = (tde->dma_state & TI1570_TX_DMA_RING_INDEX_MASK);
863 psr_addr = (psr_base + psr_index) << 2;
864
865 psr_entry = physmem_copy_u32_from_vm(d->vm,psr_addr);
866 psr_entry &= ~TI1570_TX_RING_OWN;
867 physmem_copy_u32_to_vm(d->vm,psr_addr,psr_entry);
868
869 /* Increment the packet-segmentation ring index */
870 psr_index++;
871 psr_end = d->iregs[TI1570_REG_TX_PSR_SIZE] >> 16;
872 psr_end &= TI1570_PSR_SIZE_MASK;
873
874 if (psr_index > psr_end) {
875 psr_index = 0;
876 #if DEBUG_TX_DMA
877 TI1570_LOG(d,"ti1570_scan_tx_dma_entry: PSR ring rotation "
878 "(psr_end = %u)\n",psr_end);
879 #endif
880 }
881
882 tmp = (tde->dma_state & ~TI1570_TX_DMA_RING_INDEX_MASK);
883 tmp |= (psr_index & TI1570_TX_DMA_RING_INDEX_MASK);
884 tde->dma_state = tmp;
885 }
886
887 /* Generate an interrupt if required */
888 if (tde->ctrl_buf & TI1570_TX_DMA_TCR_SELECT)
889 {
890 if (((d->iregs[TI1570_REG_STATUS] & TI1570_CFG_BP_SEL) && buf_end) ||
891 pkt_end)
892 {
893 d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_TX;
894 pci_dev_trigger_irq(d->vm,d->pci_dev_ti);
895 }
896 }
897
898 return(TRUE);
899 }
900
901 /* Analyze a TX DMA state table entry */
902 static void ti1570_scan_tx_dma_entry(struct pa_a1_data *d,m_uint32_t index)
903 {
904 int i;
905
906 for(i=0;i<TI1570_TXDMA_PASS_COUNT;i++)
907 if (!ti1570_scan_tx_dma_entry_single(d,index))
908 break;
909 }
910
911 /* Analyze the TX schedule table */
912 static void ti1570_scan_tx_sched_table(struct pa_a1_data *d)
913 {
914 m_uint32_t cw,index0,index1;
915 u_int i;
916
917 for(i=0;i<TI1570_TX_SCHED_ENTRY_COUNT>>1;i++) {
918 cw = d->tx_sched_table[i];
919
920 /* We have 2 index in TX DMA state table per word */
921 index0 = (cw >> TI1570_TX_SCHED_E0_SHIFT) & TI1570_TX_SCHED_ENTRY_MASK;
922 index1 = (cw >> TI1570_TX_SCHED_E1_SHIFT) & TI1570_TX_SCHED_ENTRY_MASK;
923
924 /* Scan the two entries (null entry => nothing to do) */
925 if (index0) ti1570_scan_tx_dma_entry(d,index0);
926 if (index1) ti1570_scan_tx_dma_entry(d,index1);
927 }
928 }
929
930 /*
931 * Read a RX buffer from the host memory.
932 */
933 static void ti1570_read_rx_buffer(struct pa_a1_data *d,m_uint32_t addr,
934 ti1570_rx_buffer_t *rx_buf)
935 {
936 physmem_copy_from_vm(d->vm,rx_buf,addr,sizeof(ti1570_rx_buffer_t));
937
938 /* byte-swapping */
939 rx_buf->reserved = vmtoh32(rx_buf->reserved);
940 rx_buf->ctrl = vmtoh32(rx_buf->ctrl);
941 rx_buf->atm_hdr = vmtoh32(rx_buf->atm_hdr);
942 rx_buf->user = vmtoh32(rx_buf->user);
943 }
944
945 /* Update the RX completion ring */
946 static void ti1570_update_rx_cring(struct pa_a1_data *d,
947 ti1570_rx_dma_entry_t *rde,
948 m_uint32_t atm_hdr,
949 m_uint32_t aal5_trailer,
950 m_uint32_t err_ind,
951 m_uint32_t fbuf_valid)
952 {
953 m_uint32_t rcr_addr,rcr_end,aal_type,ptr,val;
954 ti1570_rcr_entry_t rcre;
955
956 if (rde->ctrl & TI1570_RX_DMA_RCR_SELECT) {
957 /* RX completion ring with interrupt */
958 rcr_addr = d->iregs[TI1570_REG_RCR_WI_ADDR];
959 rcr_addr += (d->rcr_wi_pos * sizeof(rcre));
960 } else {
961 /* RX completion ring without interrupt */
962 rcr_addr = d->iregs[TI1570_REG_RCR_WOI_ADDR];
963 rcr_addr += (d->rcr_woi_pos * sizeof(rcre));
964 }
965
966 #if DEBUG_RECEIVE
967 TI1570_LOG(d,"ti1570_update_rx_cring: posting 0x%x at address 0x%x\n",
968 (rde->sp_ptr << 2),rcr_addr);
969
970 physmem_dump_vm(d->vm,rde->sp_ptr<<2,sizeof(ti1570_rx_buffer_t) >> 2);
971 #endif
972
973 /* we have a RX freeze if the buffer belongs to the host */
974 ptr = rcr_addr + OFFSET(ti1570_rcr_entry_t,fbr_entry);
975 val = physmem_copy_u32_from_vm(d->vm,ptr);
976
977 if (!(val & TI1570_RCR_OWN)) {
978 TI1570_LOG(d,"ti1570_update_rx_cring: RX freeze...\n");
979 d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_RX_FRZ;
980 return;
981 }
982
983 /* fill the RX completion ring entry and write it back to the host */
984 memset(&rcre,0,sizeof(rcre));
985
986 /* word 0: atm header from last cell received */
987 rcre.atm_hdr = atm_hdr;
988
989 /* word 1: error indicator */
990 aal_type = rde->ctrl & TI1570_RX_DMA_AAL_TYPE_MASK;
991 if (aal_type == TI1570_RX_DMA_AAL_AAL5)
992 rcre.error |= TI1570_RCR_AAL5;
993
994 rcre.error |= err_ind;
995
996 /* word 2: Start of packet */
997 if (fbuf_valid)
998 rcre.sp_addr = TI1570_RCR_VALID | rde->sp_ptr;
999
1000 /* word 3: AAL5 trailer */
1001 rcre.aal5_trailer = aal5_trailer;
1002
1003 /* word 4: OWN + error entry + free-buffer ring pointer */
1004 rcre.fbr_entry = rde->fbr_entry & TI1570_RX_DMA_FB_PTR_MASK;
1005 if (err_ind) rcre.fbr_entry |= TI1570_RCR_ERROR;
1006
1007 /* byte-swap and write this back to the host memory */
1008 rcre.atm_hdr = htonl(rcre.atm_hdr);
1009 rcre.error = htonl(rcre.error);
1010 rcre.sp_addr = htonl(rcre.sp_addr);
1011 rcre.aal5_trailer = htonl(rcre.aal5_trailer);
1012 rcre.fbr_entry = htonl(rcre.fbr_entry);
1013 physmem_copy_to_vm(d->vm,&rcre,rcr_addr,sizeof(rcre));
1014
1015 /* clear the active bit of the RX DMA entry */
1016 rde->ctrl &= ~TI1570_RX_DMA_ACT;
1017
1018 /* update the internal position pointer */
1019 if (rde->ctrl & TI1570_RX_DMA_RCR_SELECT) {
1020 rcr_end = d->iregs[TI1570_REG_RX_CRING_SIZE] & TI1570_RCR_SIZE_MASK;
1021
1022 if ((d->rcr_wi_pos++) == rcr_end)
1023 d->rcr_wi_pos = 0;
1024
1025 /* generate the appropriate IRQ */
1026 d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_RX;
1027 pci_dev_trigger_irq(d->vm,d->pci_dev_ti);
1028 } else {
1029 rcr_end = (d->iregs[TI1570_REG_RX_CRING_SIZE] >> 16);
1030 rcr_end &= TI1570_RCR_SIZE_MASK;
1031
1032 if ((d->rcr_woi_pos++) == rcr_end)
1033 d->rcr_woi_pos = 0;
1034 }
1035 }
1036
1037 /*
1038 * Acquire a free RX buffer.
1039 *
1040 * Returns FALSE if no buffer is available (buffer starvation).
1041 */
1042 static int ti1570_acquire_rx_buffer(struct pa_a1_data *d,
1043 ti1570_rx_dma_entry_t *rde,
1044 ti1570_rx_buf_holder_t *rbh,
1045 m_uint32_t atm_hdr)
1046 {
1047 ti1570_rx_fbr_entry_t *fbr_entry = NULL;
1048 m_uint32_t bp_addr,buf_addr,buf_size,buf_idx;
1049 m_uint32_t ring_index,ring_size;
1050 m_uint32_t buf_ptr,val;
1051 int fifo = FALSE;
1052
1053 /* To keep this fucking compiler quiet */
1054 ring_size = 0;
1055 buf_idx = 0;
1056
1057 if (rde->ctrl & TI1570_RX_DMA_FIFO) {
1058 bp_addr = (rde->fbr_entry & TI1570_RX_DMA_FB_PTR_MASK) << 2;
1059 buf_ptr = physmem_copy_u32_from_vm(d->vm,bp_addr);
1060 buf_size = d->iregs[TI1570_REG_TX_PSR_SIZE] & 0xFFFF;
1061 fifo = TRUE;
1062
1063 #if DEBUG_RECEIVE
1064 TI1570_LOG(d,"ti1570_acquire_rx_buffer: acquiring FIFO buffer\n");
1065 #endif
1066 }
1067 else
1068 {
1069 ring_index = rde->fbr_entry & TI1570_RX_DMA_FB_INDEX_MASK;
1070 fbr_entry = &d->rx_fbr_table[ring_index];
1071
1072 #if DEBUG_RECEIVE
1073 TI1570_LOG(d,"ti1570_acquire_rx_buffer: acquiring non-FIFO buffer, "
1074 "ring index=%u (0x%x)\n",ring_index,ring_index);
1075 #endif
1076
1077 /* Compute the number of entries in ring */
1078 ring_size = fbr_entry->ring_size & TI1570_RX_FBR_RS_MASK;
1079 ring_size >>= TI1570_RX_FBR_RS_SHIFT;
1080 ring_size = (ring_size << 4) + 15 + 1;
1081
1082 /* Compute the buffer size */
1083 buf_size = fbr_entry->ring_size & TI1570_RX_FBR_BS_MASK;
1084 buf_size >>= TI1570_RX_FBR_BS_SHIFT;
1085
1086 /* Compute the buffer address */
1087 buf_idx = fbr_entry->ring_size & TI1570_RX_FBR_IDX_MASK;
1088 bp_addr = fbr_entry->fbr_ptr + (buf_idx << 2);
1089
1090 #if DEBUG_RECEIVE
1091 TI1570_LOG(d,"ti1570_acquire_rx_buffer: ring size=%u (0x%x), "
1092 "buf size=%u ATM cells\n",ring_size,ring_size,buf_size);
1093
1094 TI1570_LOG(d,"ti1570_acquire_rx_buffer: buffer index=%u (0x%x), "
1095 "buffer ptr address = 0x%x\n",buf_idx,buf_idx,bp_addr);
1096 #endif
1097
1098 buf_ptr = physmem_copy_u32_from_vm(d->vm,bp_addr);
1099 }
1100
1101 #if DEBUG_RECEIVE
1102 TI1570_LOG(d,"ti1570_acquire_rx_buffer: buf_ptr = 0x%x\n",buf_ptr);
1103 #endif
1104
1105 /* The TI1570 must own the buffer */
1106 if (!(buf_ptr & TI1570_RX_BUFPTR_OWN)) {
1107 TI1570_LOG(d,"ti1570_acquire_rx_buffer: no free buffer available.\n");
1108 return(FALSE);
1109 }
1110
1111 /*
1112 * If we are using a ring, we have to clear the OWN bit and increment
1113 * the index field.
1114 */
1115 if (!fifo) {
1116 buf_ptr &= ~TI1570_RX_BUFPTR_OWN;
1117 physmem_copy_u32_to_vm(d->vm,bp_addr,buf_ptr);
1118
1119 if (++buf_idx == ring_size) {
1120 #if DEBUG_RECEIVE
1121 TI1570_LOG(d,"ti1570_acquire_rx_buffer: buf_idx=0x%x, "
1122 "ring_size=0x%x -> resetting buf_idx\n",
1123 buf_idx-1,ring_size);
1124 #endif
1125 buf_idx = 0;
1126 }
1127
1128 val = fbr_entry->ring_size & ~TI1570_RX_FBR_IDX_MASK;
1129 val |= buf_idx;
1130 fbr_entry->ring_size = val;
1131 }
1132
1133 /* Get the buffer address */
1134 buf_addr = (buf_ptr & TI1570_RX_BUFPTR_MASK) << 2;
1135
1136 #if DEBUG_RECEIVE
1137 TI1570_LOG(d,"ti1570_acquire_rx_buffer: buf_addr = 0x%x\n",buf_addr);
1138 #endif
1139
1140 /* Read the buffer descriptor itself and store info for caller */
1141 rbh->buf_addr = buf_addr;
1142 rbh->buf_size = buf_size;
1143 ti1570_read_rx_buffer(d,buf_addr,&rbh->rx_buf);
1144
1145 /* Clear the control field */
1146 physmem_copy_u32_to_vm(d->vm,buf_addr+OFFSET(ti1570_rx_buffer_t,ctrl),0);
1147
1148 /* Store the ATM header in data buffer */
1149 physmem_copy_u32_to_vm(d->vm,buf_addr+OFFSET(ti1570_rx_buffer_t,atm_hdr),
1150 atm_hdr);
1151 return(TRUE);
1152 }
1153
1154 /* Insert a new free buffer in a RX DMA entry */
1155 static void ti1570_insert_rx_free_buf(struct pa_a1_data *d,
1156 ti1570_rx_dma_entry_t *rde,
1157 ti1570_rx_buf_holder_t *rbh)
1158 {
1159 m_uint32_t val,aal_type;
1160
1161 aal_type = rde->ctrl & TI1570_RX_DMA_AAL_TYPE_MASK;
1162
1163 /* Set current and start of buffer addresses */
1164 rde->cb_addr = rbh->buf_addr + sizeof(ti1570_rx_buffer_t);
1165 rde->sb_addr = rbh->buf_addr >> 2;
1166
1167 /* Set the buffer length */
1168 val = rbh->buf_size;
1169
1170 if (aal_type == TI1570_RX_DMA_AAL_CNT)
1171 val |= (rde->aal5_crc & 0xFFFF) << 16;
1172
1173 rde->cb_len = val;
1174 }
1175
1176 /* Store a RX cell */
1177 static int ti1570_store_rx_cell(struct pa_a1_data *d,
1178 ti1570_rx_dma_entry_t *rde,
1179 m_uint8_t *atm_cell)
1180 {
1181 m_uint32_t aal_type,atm_hdr,aal5_trailer,pti,real_eop,pti_eop;
1182 m_uint32_t prev_buf_addr,buf_len,val,ptr,cnt;
1183 ti1570_rx_buf_holder_t rbh;
1184
1185 real_eop = pti_eop = FALSE;
1186 aal_type = rde->ctrl & TI1570_RX_DMA_AAL_TYPE_MASK;
1187
1188 /* Extract PTI from the ATM header */
1189 atm_hdr = ntohl(*(m_uint32_t *)&atm_cell[0]);
1190 pti = (atm_hdr & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1191
1192 /* PTI == 0x1 => EOP */
1193 if ((pti == 0x01) || (pti == 0x03))
1194 pti_eop = TRUE;
1195
1196 if (rde->ctrl & TI1570_RX_DMA_WAIT_EOP) {
1197 TI1570_LOG(d,"ti1570_store_rx_cell: EOP processing, not handled yet.\n");
1198 return(FALSE);
1199 }
1200
1201 /* AAL5 special processing */
1202 if (aal_type == TI1570_RX_DMA_AAL_AAL5)
1203 {
1204 /* Check that we don't exceed 1366 cells for AAL5 */
1205 /* XXX TODO */
1206 }
1207 else
1208 {
1209 /* EOP processing for non counter-based transparent-AAL packets */
1210 if ((rde->ctrl & TI1570_RX_DMA_WAIT_EOP) && pti_eop)
1211 {
1212 /* XXX TODO */
1213 }
1214 }
1215
1216 /* do we have enough room in buffer ? */
1217 buf_len = rde->cb_len & TI1570_RX_DMA_CB_LEN_MASK;
1218
1219 if (!buf_len) {
1220 prev_buf_addr = rde->sb_addr << 2;
1221
1222 /* acquire a new free buffer */
1223 if (!ti1570_acquire_rx_buffer(d,rde,&rbh,atm_hdr)) {
1224 rde->ctrl |= TI1570_RX_DMA_WAIT_EOP;
1225 return(FALSE);
1226 }
1227
1228 /* insert the free buffer in the RX DMA structure */
1229 ti1570_insert_rx_free_buf(d,rde,&rbh);
1230
1231 /* chain the buffers (keep SOP/EOP bits intact) */
1232 ptr = prev_buf_addr + OFFSET(ti1570_rx_buffer_t,ctrl);
1233
1234 val = physmem_copy_u32_from_vm(d->vm,ptr);
1235 val |= rde->sb_addr;
1236 physmem_copy_u32_to_vm(d->vm,ptr,val);
1237
1238 /* read the new buffer length */
1239 buf_len = rde->cb_len & TI1570_RX_DMA_CB_LEN_MASK;
1240 }
1241
1242 /* copy the ATM payload */
1243 #if DEBUG_RECEIVE
1244 TI1570_LOG(d,"ti1570_store_rx_cell: storing cell payload at 0x%x "
1245 "(buf_addr=0x%x)\n",rde->cb_addr,rde->sb_addr << 2);
1246 #endif
1247
1248 physmem_copy_to_vm(d->vm,&atm_cell[ATM_HDR_SIZE],
1249 rde->cb_addr,ATM_PAYLOAD_SIZE);
1250 rde->cb_addr += ATM_PAYLOAD_SIZE;
1251
1252 /* update the current buffer length */
1253 val = rde->cb_len & ~TI1570_RX_DMA_CB_LEN_MASK;
1254 rde->cb_len = val | (--buf_len);
1255
1256 #if DEBUG_RECEIVE
1257 TI1570_LOG(d,"ti1570_store_rx_cell: new rde->cb_len = 0x%x, "
1258 "buf_len=0x%x\n",rde->cb_len,buf_len);
1259 #endif
1260
1261 /* determine if this is the end of the packet (EOP) */
1262 if (aal_type == TI1570_RX_DMA_AAL_CNT)
1263 {
1264 /* counter-based tranparent-AAL packets */
1265 cnt = rde->cb_len & TI1570_RX_DMA_TR_CNT_MASK;
1266 cnt >>= TI1570_RX_DMA_TR_CNT_SHIFT;
1267
1268 /* if the counter reaches 0, this is the EOP */
1269 if (--cnt == 0)
1270 real_eop = TRUE;
1271
1272 val = rde->cb_len & ~TI1570_RX_DMA_TR_CNT_MASK;
1273 val |= cnt << TI1570_RX_DMA_TR_CNT_SHIFT;
1274 }
1275 else {
1276 /* PTI-based transparent AAL packets or AAL5 */
1277 if (pti_eop)
1278 real_eop = TRUE;
1279 }
1280
1281 if (real_eop) {
1282 /* mark the buffer as EOP */
1283 ptr = (rde->sb_addr << 2) + OFFSET(ti1570_rx_buffer_t,ctrl);
1284 val = physmem_copy_u32_from_vm(d->vm,ptr);
1285 val |= TI1570_RX_BUFFER_EOP;
1286 physmem_copy_u32_to_vm(d->vm,ptr,val);
1287
1288 /* get the aal5 trailer */
1289 aal5_trailer = ntohl(*(m_uint32_t *)&atm_cell[ATM_AAL5_TRAILER_POS]);
1290
1291 /* post the entry into the appropriate RX completion ring */
1292 ti1570_update_rx_cring(d,rde,atm_hdr,aal5_trailer,0,TRUE);
1293 }
1294
1295 return(TRUE);
1296 }
1297
1298 /* Handle a received ATM cell */
1299 static int ti1570_handle_rx_cell(netio_desc_t *nio,
1300 u_char *atm_cell,ssize_t cell_len,
1301 struct pa_a1_data *d)
1302 {
1303 m_uint32_t atm_hdr,vpi,vci,vci_idx,vci_mask;
1304 m_uint32_t vci_max,rvd_entry,bptr,pti,ptr;
1305 ti1570_rx_dma_entry_t *rde = NULL;
1306 ti1570_rx_buf_holder_t rbh;
1307
1308 if (cell_len != ATM_CELL_SIZE) {
1309 TI1570_LOG(d,"invalid RX cell size (%ld)\n",(long)cell_len);
1310 return(FALSE);
1311 }
1312
1313 /* Extract the VPI/VCI used as index in the RX VPI/VCI DMA pointer table */
1314 atm_hdr = ntohl(*(m_uint32_t *)&atm_cell[0]);
1315 vpi = (atm_hdr & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1316 vci = (atm_hdr & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1317 pti = (atm_hdr & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1318
1319 #if DEBUG_RECEIVE
1320 TI1570_LOG(d,"ti1570_handle_rx_cell: received cell with VPI/VCI=%u/%u\n",
1321 vpi,vci);
1322 #endif
1323
1324 /* Get the entry corresponding to this VPI in RX VPI/VCI dma ptr table */
1325 rvd_entry = d->rx_vpi_vci_dma_table[vpi];
1326
1327 if (!(rvd_entry & TI1570_RX_VPI_ENABLE)) {
1328 TI1570_LOG(d,"ti1570_handle_rx_cell: received cell with "
1329 "unknown VPI %u (VCI=%u)\n",vpi,vci);
1330 return(FALSE);
1331 }
1332
1333 /*
1334 * Special routing for OAM F4 cells:
1335 * - VCI 3 : OAM F4 segment cell
1336 * - VCI 4 : OAM F4 end-to-end cell
1337 */
1338 if ((vci == 3) || (vci == 4))
1339 rde = &d->rx_dma_table[2];
1340 else {
1341 if ((atm_hdr & ATM_PTI_NETWORK) != 0) {
1342 switch(pti) {
1343 case 0x04: /* OAM F5-segment cell */
1344 case 0x05: /* OAM F5 end-to-end cell */
1345 rde = &d->rx_dma_table[0];
1346 break;
1347
1348 case 0x06:
1349 case 0x07:
1350 rde = &d->rx_dma_table[1];
1351 break;
1352 }
1353 } else {
1354 /*
1355 * Standard VPI/VCI.
1356 * Apply the VCI mask if we don't have an OAM cell.
1357 */
1358 if (!(atm_hdr & ATM_PTI_NETWORK)) {
1359 vci_mask = d->iregs[TI1570_REG_TX_RX_FIFO] >> 16;
1360 vci_idx = vci & (~vci_mask);
1361
1362 vci_max = rvd_entry & TI1570_RX_VCI_RANGE_MASK;
1363
1364 if (vci_idx > vci_max) {
1365 TI1570_LOG(d,"ti1570_handle_rx_cell: out-of-range VCI %u "
1366 "(VPI=%u,vci_mask=%u,vci_max=%u)\n",
1367 vci,vpi,vci_mask,vci_max);
1368 return(FALSE);
1369 }
1370
1371 #if DEBUG_RECEIVE
1372 TI1570_LOG(d,"ti1570_handle_rx_cell: VPI/VCI=%u/%u, "
1373 "vci_mask=0x%x, vci_idx=%u (0x%x), vci_max=%u (0x%x)\n",
1374 vpi,vci,vci_mask,vci_idx,vci_idx,vci_max,vci_max);
1375 #endif
1376 bptr = (rvd_entry & TI1570_RX_BASE_PTR_MASK);
1377 bptr >>= TI1570_RX_BASE_PTR_SHIFT;
1378 bptr = (bptr + vci) * sizeof(ti1570_rx_dma_entry_t);
1379
1380 if (bptr < TI1570_RX_DMA_TABLE_OFFSET) {
1381 TI1570_LOG(d,"ti1570_handle_rx_cell: inconsistency in "
1382 "RX VPI/VCI table, VPI/VCI=%u/u, bptr=0x%x\n",
1383 vpi,vci,bptr);
1384 return(FALSE);
1385 }
1386
1387 bptr -= TI1570_RX_DMA_TABLE_OFFSET;
1388 rde = &d->rx_dma_table[bptr / sizeof(ti1570_rx_dma_entry_t)];
1389 }
1390 }
1391 }
1392
1393 if (!rde) {
1394 TI1570_LOG(d,"ti1570_handle_rx_cell: no RX DMA table entry found!\n");
1395 return(FALSE);
1396 }
1397
1398 /* The entry must be active */
1399 if (!(rde->fbr_entry & TI1570_RX_DMA_ON))
1400 return(FALSE);
1401
1402 /* Is this the start of a new packet ? */
1403 if (!(rde->ctrl & TI1570_RX_DMA_ACT))
1404 {
1405 /* Try to acquire a free buffer */
1406 if (!ti1570_acquire_rx_buffer(d,rde,&rbh,atm_hdr)) {
1407 rde->ctrl |= TI1570_RX_DMA_WAIT_EOP;
1408 return(FALSE);
1409 }
1410
1411 /* Insert the free buffer in the RX DMA structure */
1412 ti1570_insert_rx_free_buf(d,rde,&rbh);
1413 rde->sp_ptr = rde->sb_addr;
1414
1415 /* Mark the RX buffer as the start of packet (SOP) */
1416 ptr = (rde->sb_addr << 2) + OFFSET(ti1570_rx_buffer_t,ctrl);
1417 physmem_copy_u32_to_vm(d->vm,ptr,TI1570_RX_BUFFER_SOP);
1418
1419 /* Set ACT bit for the DMA channel */
1420 rde->ctrl |= TI1570_RX_DMA_ACT;
1421 }
1422
1423 /* Store the received cell */
1424 ti1570_store_rx_cell(d,rde,atm_cell);
1425 return(TRUE);
1426 }
1427
1428 /*
1429 * pci_ti1570_read()
1430 */
1431 static m_uint32_t pci_ti1570_read(cpu_mips_t *cpu,struct pci_device *dev,
1432 int reg)
1433 {
1434 struct pa_a1_data *d = dev->priv_data;
1435
1436 #if DEBUG_ACCESS
1437 TI1570_LOG(d,"pci_ti1570_read: read reg 0x%x\n",reg);
1438 #endif
1439
1440 switch(reg) {
1441 case PCI_REG_BAR0:
1442 return(d->dev->phys_addr);
1443 default:
1444 return(0);
1445 }
1446 }
1447
1448 /*
1449 * pci_ti1570_write()
1450 */
1451 static void pci_ti1570_write(cpu_mips_t *cpu,struct pci_device *dev,
1452 int reg,m_uint32_t value)
1453 {
1454 struct pa_a1_data *d = dev->priv_data;
1455
1456 #if DEBUG_ACCESS
1457 TI1570_LOG(d,"pci_ti1570_write: write reg 0x%x, value 0x%x\n",reg,value);
1458 #endif
1459
1460 switch(reg) {
1461 case PCI_REG_BAR0:
1462 vm_map_device(cpu->vm,d->dev,(m_uint64_t)value);
1463 TI1570_LOG(d,"registers are mapped at 0x%x\n",value);
1464 break;
1465 }
1466 }
1467
1468 /*
1469 * pci_plx9060es_read()
1470 */
1471 static m_uint32_t pci_plx9060es_read(cpu_mips_t *cpu,struct pci_device *dev,
1472 int reg)
1473 {
1474 #if DEBUG_ACCESS
1475 TI1570_LOG(d,"PLX9060ES","read reg 0x%x\n",reg);
1476 #endif
1477 switch(reg) {
1478 default:
1479 return(0);
1480 }
1481 }
1482
1483 /*
1484 * pci_plx9060es_write()
1485 */
1486 static void pci_plx9060es_write(cpu_mips_t *cpu,struct pci_device *dev,
1487 int reg,m_uint32_t value)
1488 {
1489 #if DEBUG_ACCESS
1490 TI1570_LOG(d,"PLX9060ES","write reg 0x%x, value 0x%x\n",reg,value);
1491 #endif
1492
1493 switch(reg) {
1494 }
1495 }
1496
1497 /* Reset the TI1570 */
1498 static void ti1570_reset(struct pa_a1_data *d,int clear_ctrl_mem)
1499 {
1500 ti1570_clear_tx_fifo(d);
1501
1502 d->tcr_wi_pos = d->tcr_woi_pos = 0;
1503 d->rcr_wi_pos = d->rcr_woi_pos = 0;
1504
1505 if (clear_ctrl_mem)
1506 memset(d->ctrl_mem_ptr,0,TI1570_CTRL_MEM_SIZE);
1507 }
1508
1509 /*
1510 * dev_c7200_pa_a1_init()
1511 *
1512 * Add a PA-A1 port adapter into specified slot.
1513 */
1514 int dev_c7200_pa_a1_init(c7200_t *router,char *name,u_int pa_bay)
1515 {
1516 struct pci_device *pci_dev_ti,*pci_dev_plx;
1517 struct pa_a1_data *d;
1518 struct vdevice *dev;
1519 m_uint8_t *p;
1520
1521 /* Allocate the private data structure for TI1570 chip */
1522 if (!(d = malloc(sizeof(*d)))) {
1523 fprintf(stderr,"%s (TI1570): out of memory\n",name);
1524 return(-1);
1525 }
1526
1527 memset(d,0,sizeof(*d));
1528
1529 /* Set the EEPROM */
1530 c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-A1"));
1531
1532 /* Add PCI device TI1570 */
1533 pci_dev_ti = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
1534 TI1570_PCI_VENDOR_ID,TI1570_PCI_PRODUCT_ID,
1535 0,0,C7200_NETIO_IRQ,d,
1536 NULL,pci_ti1570_read,pci_ti1570_write);
1537
1538 if (!pci_dev_ti) {
1539 fprintf(stderr,"%s (TI1570): unable to create PCI device TI1570.\n",
1540 name);
1541 return(-1);
1542 }
1543
1544 /* Add PCI device PLX9060ES */
1545 pci_dev_plx = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
1546 PLX_9060ES_PCI_VENDOR_ID,
1547 PLX_9060ES_PCI_PRODUCT_ID,
1548 1,0,C7200_NETIO_IRQ,d,
1549 NULL,pci_plx9060es_read,pci_plx9060es_write);
1550
1551 if (!pci_dev_plx) {
1552 fprintf(stderr,"%s (PLX_9060ES): unable to create PCI device "
1553 "PLX 9060ES.\n",name);
1554 return(-1);
1555 }
1556
1557 /* Create the TI1570 structure */
1558 d->name = name;
1559 d->vm = router->vm;
1560 d->pci_dev_ti = pci_dev_ti;
1561 d->pci_dev_plx = pci_dev_plx;
1562
1563 /* Allocate the control memory */
1564 if (!(d->ctrl_mem_ptr = malloc(TI1570_CTRL_MEM_SIZE))) {
1565 fprintf(stderr,"%s (PA-A1): unable to create control memory.\n",name);
1566 return(-1);
1567 }
1568
1569 /* Standard tables for the TI1570 */
1570 p = (m_uint8_t *)d->ctrl_mem_ptr;
1571
1572 d->iregs = (m_uint32_t *)(p + TI1570_INTERNAL_REGS_OFFSET);
1573 d->tx_sched_table = (m_uint32_t *)(p + TI1570_TX_SCHED_OFFSET);
1574 d->tx_dma_table = (ti1570_tx_dma_entry_t *)(p + TI1570_TX_DMA_TABLE_OFFSET);
1575 d->rx_vpi_vci_dma_table = (m_uint32_t *)(p+TI1570_RX_DMA_PTR_TABLE_OFFSET);
1576 d->rx_dma_table = (ti1570_rx_dma_entry_t *)(p + TI1570_RX_DMA_TABLE_OFFSET);
1577 d->rx_fbr_table = (ti1570_rx_fbr_entry_t *)(p + TI1570_FREE_BUFFERS_OFFSET);
1578
1579 ti1570_reset(d,TRUE);
1580
1581 /* Create the device itself */
1582 if (!(dev = dev_create(name))) {
1583 fprintf(stderr,"%s (PA-A1): unable to create device.\n",name);
1584 return(-1);
1585 }
1586
1587 dev->phys_addr = 0;
1588 dev->phys_len = 0x200000;
1589 dev->handler = dev_pa_a1_access;
1590
1591 /* Store device info */
1592 dev->priv_data = d;
1593 d->dev = dev;
1594
1595 /* Store device info into the router structure */
1596 return(c7200_pa_set_drvinfo(router,pa_bay,d));
1597 }
1598
1599 /* Remove a PA-A1 from the specified slot */
1600 int dev_c7200_pa_a1_shutdown(c7200_t *router,u_int pa_bay)
1601 {
1602 struct c7200_pa_bay *bay;
1603 struct pa_a1_data *d;
1604
1605 if (!(bay = c7200_pa_get_info(router,pa_bay)))
1606 return(-1);
1607
1608 d = bay->drv_info;
1609
1610 /* Remove the PA EEPROM */
1611 c7200_pa_unset_eeprom(router,pa_bay);
1612
1613 /* Remove the PCI devices */
1614 pci_dev_remove(d->pci_dev_ti);
1615 pci_dev_remove(d->pci_dev_plx);
1616
1617 /* Remove the device from the VM address space */
1618 vm_unbind_device(router->vm,d->dev);
1619 cpu_group_rebuild_mts(router->vm->cpu_group);
1620
1621 /* Free the control memory */
1622 free(d->ctrl_mem_ptr);
1623
1624 /* Free the device structure itself */
1625 free(d->dev);
1626 free(d);
1627 return(0);
1628 }
1629
1630 /* Bind a Network IO descriptor to a specific port */
1631 int dev_c7200_pa_a1_set_nio(c7200_t *router,u_int pa_bay,u_int port_id,
1632 netio_desc_t *nio)
1633 {
1634 struct pa_a1_data *d;
1635
1636 if ((port_id > 0) || !(d = c7200_pa_get_drvinfo(router,pa_bay)))
1637 return(-1);
1638
1639 if (d->nio != NULL)
1640 return(-1);
1641
1642 d->nio = nio;
1643 d->tx_tid = ptask_add((ptask_callback)ti1570_scan_tx_sched_table,d,NULL);
1644 netio_rxl_add(nio,(netio_rx_handler_t)ti1570_handle_rx_cell,d,NULL);
1645 return(0);
1646 }
1647
1648 /* Unbind a Network IO descriptor to a specific port */
1649 int dev_c7200_pa_a1_unset_nio(c7200_t *router,u_int pa_bay,u_int port_id)
1650 {
1651 struct pa_a1_data *d;
1652
1653 if ((port_id > 0) || !(d = c7200_pa_get_drvinfo(router,pa_bay)))
1654 return(-1);
1655
1656 if (d->nio) {
1657 ptask_remove(d->tx_tid);
1658 netio_rxl_remove(d->nio);
1659 d->nio = NULL;
1660 }
1661 return(0);
1662 }
1663
1664 /* PA-A1 driver */
1665 struct c7200_pa_driver dev_c7200_pa_a1_driver = {
1666 "PA-A1", 1,
1667 dev_c7200_pa_a1_init,
1668 dev_c7200_pa_a1_shutdown,
1669 dev_c7200_pa_a1_set_nio,
1670 dev_c7200_pa_a1_unset_nio,
1671 NULL,
1672 };

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