/[dynamips]/upstream/dynamips-0.2.6-RC1/dev_sb1_pci.c
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Annotation of /upstream/dynamips-0.2.6-RC1/dev_sb1_pci.c

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Revision 1 - (hide annotations)
Sat Oct 6 16:01:44 2007 UTC (11 years, 9 months ago) by dpavlin
Original Path: upstream/dynamips-0.2.5/dev_sb1_pci.c
File MIME type: text/plain
File size: 3857 byte(s)
import 0.2.5 from upstream

1 dpavlin 1 /*
2     * Cisco C7200 (Predator) Simulation Platform.
3     * Copyright (c) 2006 Christophe Fillot. All rights reserved.
4     *
5     * PCI configuration space for SB-1 processor.
6     */
7    
8     #include <stdio.h>
9     #include <stdlib.h>
10     #include <string.h>
11     #include <time.h>
12     #include <errno.h>
13    
14     #include "mips64.h"
15     #include "dynamips.h"
16     #include "memory.h"
17     #include "device.h"
18    
19     #define DEBUG_ACCESS 0
20    
21     /* Sibyte PCI ID */
22     #define SB1_PCI_VENDOR_ID 0x166D
23    
24     /* SB-1 PCI private data */
25     struct sb1_pci_data {
26     vm_obj_t vm_obj;
27     struct vdevice dev;
28     struct pci_bus *pci_bus;
29    
30     /* PCI configuration (Bus 0, Device 0) */
31     struct pci_device *pci_cfg_dev;
32    
33     /* HyperTransport configuration (Bus 0, Device 1) */
34     struct pci_device *ht_cfg_dev;
35     };
36    
37     /*
38     * sb1_pci_cfg_read()
39     *
40     * PCI Configuration (Bus 0, Device 0).
41     */
42     static m_uint32_t sb1_pci_cfg_read(cpu_mips_t *cpu,struct pci_device *dev,
43     int reg)
44     {
45     switch(reg) {
46     case 0x08:
47     return(0x06000002);
48     default:
49     return(0);
50     }
51     }
52    
53     /*
54     * sb1_ht_cfg_read()
55     *
56     * HyperTransport Configuration (Bus 0, Device 1).
57     */
58     static m_uint32_t sb1_ht_cfg_read(cpu_mips_t *cpu,struct pci_device *dev,
59     int reg)
60     {
61     switch(reg) {
62     case 0x08:
63     return(0x06000002);
64     case 0x44:
65     return(1<<5); /* HyperTransport OK */
66     default:
67     return(0);
68     }
69     }
70    
71     /*
72     * dev_sb1_pci_access()
73     */
74     void *dev_sb1_pci_access(cpu_mips_t *cpu,struct vdevice *dev,
75     m_uint32_t offset,u_int op_size,u_int op_type,
76     m_uint64_t *data)
77     {
78     struct sb1_pci_data *d = dev->priv_data;
79    
80     #if DEBUG_ACCESS
81     if (op_type == MTS_READ)
82     cpu_log(cpu,dev->name,"read access to offset = 0x%x, pc = 0x%llx\n",
83     offset,cpu->pc);
84     else
85     cpu_log(cpu,dev->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
86     "val = 0x%llx\n",offset,cpu->pc,*data);
87     #endif
88    
89     if (op_type == MTS_READ)
90     *data = 0;
91    
92     d->pci_bus->pci_addr = offset;
93     pci_dev_data_handler(cpu,d->pci_bus,op_type,FALSE,data);
94     return NULL;
95     }
96    
97     /* Shutdown the PCI bus configuration zone */
98     void dev_sb1_pci_shutdown(vm_instance_t *vm,struct sb1_pci_data *d)
99     {
100     if (d != NULL) {
101     /* Remove the device */
102     dev_remove(vm,&d->dev);
103    
104     /* Free the structure itself */
105     free(d);
106     }
107     }
108    
109     /* Create the SB-1 PCI bus configuration zone */
110     int dev_sb1_pci_init(vm_instance_t *vm,char *name,m_uint64_t paddr)
111     {
112     struct sb1_pci_data *d;
113    
114     /* allocate the private data structure */
115     if (!(d = malloc(sizeof(*d)))) {
116     fprintf(stderr,"SB1_PCI: unable to create device.\n");
117     return(-1);
118     }
119    
120     memset(d,0,sizeof(*d));
121     d->pci_bus = vm->pci_bus[0];
122    
123     vm_object_init(&d->vm_obj);
124     d->vm_obj.name = name;
125     d->vm_obj.data = d;
126     d->vm_obj.shutdown = (vm_shutdown_t)dev_sb1_pci_shutdown;
127    
128     dev_init(&d->dev);
129     d->dev.name = name;
130     d->dev.priv_data = d;
131     d->dev.phys_addr = paddr;
132     d->dev.phys_len = 1 << 24;
133     d->dev.handler = dev_sb1_pci_access;
134    
135     /* PCI configuration header on Bus 0, Device 0 */
136     d->pci_cfg_dev = pci_dev_add(d->pci_bus,"sb1_pci_cfg",
137     SB1_PCI_VENDOR_ID,0x0001,0,0,-1,NULL,
138     NULL,sb1_pci_cfg_read,NULL);
139    
140     /* Create the HyperTransport bus #1 */
141     vm->pci_bus_pool[28] = pci_bus_create("HT bus #1",-1);
142    
143     /* HyperTransport configuration header on Bus 0, Device 1 */
144     d->ht_cfg_dev = pci_bridge_create_dev(d->pci_bus,"sb1_ht_cfg",
145     SB1_PCI_VENDOR_ID,0x0002,
146     1,0,vm->pci_bus_pool[28],
147     sb1_ht_cfg_read,NULL);
148    
149     /* Map this device to the VM */
150     vm_bind_device(vm,&d->dev);
151     vm_object_add(vm,&d->vm_obj);
152     return(0);
153     }

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