/[dynamips]/upstream/dynamips-0.2.5/dynamips.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /upstream/dynamips-0.2.5/dynamips.h

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Revision 1 - (show annotations)
Sat Oct 6 16:01:44 2007 UTC (12 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 5036 byte(s)
import 0.2.5 from upstream

1 /*
2 * Cisco 7200 (Predator) simulation platform.
3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4 */
5
6 #ifndef __DYNAMIPS_H__
7 #define __DYNAMIPS_H__
8
9 #include <libelf.h>
10
11 #include "utils.h"
12
13 /* Debugging flags */
14 #define DEBUG_BLOCK_SCAN 0
15 #define DEBUG_BLOCK_COMPILE 0
16 #define DEBUG_BLOCK_PATCH 0
17 #define DEBUG_BLOCK_CHUNK 0
18 #define DEBUG_BLOCK_TIMESTAMP 0 /* block timestamping (little overhead) */
19 #define DEBUG_SYM_TREE 0 /* use symbol tree (slow) */
20 #define DEBUG_MTS_MAP_DEV 0
21 #define DEBUG_MTS_MAP_VIRT 0
22 #define DEBUG_MTS_ACC_U 1 /* undefined memory */
23 #define DEBUG_MTS_ACC_T 1 /* tlb exception */
24 #define DEBUG_MTS_ACC_AE 1 /* address error exception */
25 #define DEBUG_MTS_DEV 0 /* debugging for device access */
26 #define DEBUG_MTS_STATS 1 /* MTS64 cache performance */
27 #define DEBUG_PERF_COUNTER 0 /* Performance counter */
28 #define DEBUG_TLB_ACTIVITY 0
29 #define DEBUG_SYSCALL 0
30 #define DEBUG_CACHE 0
31 #define DEBUG_JR0 0 /* Debug register jumps to 0 */
32
33 /* Feature flags */
34 #define MEMLOG_ENABLE 0 /* Memlogger (MTS ASM must be disabled) */
35 #define BREAKPOINT_ENABLE 0 /* Virtual Breakpoints */
36 #define NJM_STATS_ENABLE 1 /* Non-JIT mode stats (little overhead) */
37 #define MTSASM_ENABLE 1 /* Optimized-assembly MTS */
38
39 /* Size of executable page area (in Mb) */
40 #ifndef __CYGWIN__
41 #define MIPS_EXEC_AREA_SIZE 64
42 #else
43 #define MIPS_EXEC_AREA_SIZE 16
44 #endif
45
46 /* Buffer size for JIT code generation */
47 #define MIPS_JIT_BUFSIZE 32768
48
49 /* Maximum number of X86 chunks */
50 #define INSN_MAX_CHUNKS 32
51
52 /* Translated block function pointer */
53 typedef m_uint64_t (*insn_tblock_fptr)(void);
54
55 /* Instruction jump patch */
56 struct insn_patch {
57 u_char *jit_insn;
58 m_uint64_t mips_pc;
59 };
60
61 /* Instruction patch table */
62 #define INSN_PATCH_TABLE_SIZE 32
63
64 struct insn_patch_table {
65 struct insn_patch patches[INSN_PATCH_TABLE_SIZE];
66 u_int cur_patch;
67 struct insn_patch_table *next;
68 };
69
70 /* Exec page */
71 struct insn_exec_page {
72 u_char *ptr;
73 insn_exec_page_t *next;
74 };
75
76 /* Instruction block */
77 struct insn_block {
78 m_uint64_t start_pc;
79 u_char **jit_insn_ptr;
80 m_uint64_t acc_count;
81 m_uint32_t phys_page;
82 mips_insn_t *mips_code;
83 u_int mips_trans_pos;
84 u_int jit_chunk_pos;
85 u_char *jit_ptr;
86 insn_exec_page_t *jit_buffer;
87 insn_exec_page_t *jit_chunks[INSN_MAX_CHUNKS];
88 struct insn_patch_table *patch_table;
89 insn_block_t *prev,*next;
90 #if DEBUG_BLOCK_TIMESTAMP
91 m_uint64_t tm_first_use,tm_last_use;
92 #endif
93 };
94
95 /* MIPS instruction recognition */
96 struct insn_tag {
97 int (*emit)(cpu_mips_t *cpu,struct insn_block *,mips_insn_t);
98 m_uint32_t mask,value;
99 int delay_slot;
100 };
101
102 /* MIPS jump instruction (for block scan) */
103 struct insn_jump {
104 char *name;
105 m_uint32_t mask,value;
106 int offset_bits;
107 int relative;
108 };
109
110 /* Symbol */
111 struct symbol {
112 m_uint64_t addr;
113 char name[0];
114 };
115
116 /* ROM identification tag */
117 #define ROM_ID 0x1e94b3df
118
119 /* Global log file */
120 extern FILE *log_file;
121
122 /* Software version */
123 extern const char *sw_version;
124
125 /* Get the JIT instruction pointer in a compiled block */
126 static forced_inline
127 u_char *insn_block_get_jit_ptr(struct insn_block *block,m_uint64_t vaddr)
128 {
129 m_uint64_t offset;
130
131 offset = (vaddr - block->start_pc) >> 2;
132 return(block->jit_insn_ptr[offset]);
133 }
134
135 /* Check if there are pending IRQ */
136 extern void mips64_check_pending_irq(struct insn_block *b);
137
138 /* Initialize instruction lookup table */
139 void mips64_jit_create_ilt(void);
140
141 /* Initialize the JIT structure */
142 int mips64_jit_init(cpu_mips_t *cpu);
143
144 /* Flush the JIT */
145 u_int mips64_jit_flush(cpu_mips_t *cpu,u_int threshold);
146
147 /* Shutdown the JIT */
148 void mips64_jit_shutdown(cpu_mips_t *cpu);
149
150 /* Find the JIT code emitter for the specified MIPS instruction */
151 struct insn_tag *insn_tag_find(mips_insn_t ins);
152
153 /* Check if the specified MIPS instruction is a jump */
154 struct insn_jump *insn_jump_find(mips_insn_t ins);
155
156 /* Fetch a MIPS instruction and emit corresponding x86 translated code */
157 struct insn_tag *insn_fetch_and_emit(cpu_mips_t *cpu,struct insn_block *block,
158 int delay_slot);
159
160 /* Record a patch to apply in a compiled block */
161 int insn_block_record_patch(struct insn_block *block,u_char *x86_ptr,
162 m_uint64_t vaddr);
163
164 /* Free an instruction block */
165 void insn_block_free(cpu_mips_t *cpu,insn_block_t *block,int list_removal);
166
167 /* Tree comparison function */
168 int insn_block_cmp(m_uint64_t *vaddr,struct insn_block *b);
169
170 /* Check if the specified address belongs to the specified block */
171 int insn_block_local_addr(struct insn_block *block,m_uint64_t vaddr,
172 u_char **x86_addr);
173
174 /* Execute a compiled MIPS code */
175 void *insn_block_execute(cpu_mips_t *cpu);
176
177 /* Dump the instruction block tree */
178 void insn_block_dump_tree(cpu_mips_t *cpu);
179
180 /* Delete all objects */
181 void dynamips_reset(void);
182
183 #endif

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