/[dynamips]/trunk/ppc32_amd64_trans.c
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Diff of /trunk/ppc32_amd64_trans.c

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upstream/dynamips-0.2.7/ppc32_amd64_trans.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC upstream/dynamips-0.2.8-RC1/ppc32_amd64_trans.c revision 11 by dpavlin, Sat Oct 6 16:33:40 2007 UTC
# Line 390  static void ppc32_emit_memop(cpu_ppc_t * Line 390  static void ppc32_emit_memop(cpu_ppc_t *
390                               int op,int base,int offset,int target,int update)                               int op,int base,int offset,int target,int update)
391  {  {
392     m_uint32_t val = sign_extend(offset,16);     m_uint32_t val = sign_extend(offset,16);
    u_char *test1;  
393     jit_op_t *iop;     jit_op_t *iop;
394    
395     /*     /*
# Line 424  static void ppc32_emit_memop(cpu_ppc_t * Line 423  static void ppc32_emit_memop(cpu_ppc_t *
423     /* Call memory function */     /* Call memory function */
424     amd64_call_membase(iop->ob_ptr,AMD64_R15,MEMOP_OFFSET(op));     amd64_call_membase(iop->ob_ptr,AMD64_R15,MEMOP_OFFSET(op));
425    
    /* Exception ? */  
    amd64_test_reg_reg_size(iop->ob_ptr,AMD64_RAX,AMD64_RAX,4);  
    test1 = iop->ob_ptr;  
    amd64_branch8(iop->ob_ptr, X86_CC_Z, 0, 1);  
    ppc32_jit_tcb_push_epilog(&iop->ob_ptr);  
    amd64_patch(test1,iop->ob_ptr);  
   
426     if (update)     if (update)
427        ppc32_store_gpr(&iop->ob_ptr,base,AMD64_R14);        ppc32_store_gpr(&iop->ob_ptr,base,AMD64_R14);
428  }  }
# Line 439  static void ppc32_emit_memop(cpu_ppc_t * Line 431  static void ppc32_emit_memop(cpu_ppc_t *
431  static void ppc32_emit_memop_idx(cpu_ppc_t *cpu,ppc32_jit_tcb_t *b,  static void ppc32_emit_memop_idx(cpu_ppc_t *cpu,ppc32_jit_tcb_t *b,
432                                   int op,int ra,int rb,int target,int update)                                   int op,int ra,int rb,int target,int update)
433  {  {
    u_char *test1;  
434     jit_op_t *iop;     jit_op_t *iop;
435    
436     /*     /*
# Line 473  static void ppc32_emit_memop_idx(cpu_ppc Line 464  static void ppc32_emit_memop_idx(cpu_ppc
464     /* Call memory function */     /* Call memory function */
465     amd64_call_membase(iop->ob_ptr,AMD64_R15,MEMOP_OFFSET(op));     amd64_call_membase(iop->ob_ptr,AMD64_R15,MEMOP_OFFSET(op));
466    
    /* Exception ? */  
    amd64_test_reg_reg_size(iop->ob_ptr,AMD64_RAX,AMD64_RAX,4);  
    test1 = iop->ob_ptr;  
    amd64_branch8(iop->ob_ptr, X86_CC_Z, 0, 1);  
    ppc32_jit_tcb_push_epilog(&iop->ob_ptr);  
    amd64_patch(test1,iop->ob_ptr);  
   
467     if (update)     if (update)
468        ppc32_store_gpr(&iop->ob_ptr,ra,AMD64_R14);        ppc32_store_gpr(&iop->ob_ptr,ra,AMD64_R14);
469  }  }
# Line 524  static void ppc32_emit_memop_fast(cpu_pp Line 508  static void ppc32_emit_memop_fast(cpu_pp
508                                    memop_fast_access op_handler)                                    memop_fast_access op_handler)
509  {    {  
510     m_uint32_t val = sign_extend(offset,16);     m_uint32_t val = sign_extend(offset,16);
511     u_char *test1,*test2,*p_exception,*p_exit;     u_char *test1,*test2,*p_exit;
512     jit_op_t *iop;     jit_op_t *iop;
513    
514     /*     /*
# Line 601  static void ppc32_emit_memop_fast(cpu_pp Line 585  static void ppc32_emit_memop_fast(cpu_pp
585     /* Call memory access function */     /* Call memory access function */
586     amd64_call_membase(iop->ob_ptr,AMD64_R15,MEMOP_OFFSET(opcode));     amd64_call_membase(iop->ob_ptr,AMD64_R15,MEMOP_OFFSET(opcode));
587    
    /* Exception ? */  
    amd64_test_reg_reg_size(iop->ob_ptr,AMD64_RAX,AMD64_RAX,4);  
    p_exception = iop->ob_ptr;  
    amd64_branch8(iop->ob_ptr, X86_CC_Z, 0, 1);  
    ppc32_jit_tcb_push_epilog(&iop->ob_ptr);  
   
588     amd64_patch(p_exit,iop->ob_ptr);     amd64_patch(p_exit,iop->ob_ptr);
    amd64_patch(p_exception,iop->ob_ptr);  
589  }  }
590    
591  /* Emit unhandled instruction code */  /* Emit unhandled instruction code */
# Line 655  void ppc32_emit_breakpoint(cpu_ppc_t *cp Line 632  void ppc32_emit_breakpoint(cpu_ppc_t *cp
632  }  }
633    
634  /* Increment the number of executed instructions (performance debugging) */  /* Increment the number of executed instructions (performance debugging) */
635  void ppc32_inc_perf_counter(ppc32_jit_tcb_t *b)  void ppc32_inc_perf_counter(cpu_ppc_t *cpu)
636  {  {    
637     amd64_inc_membase(b->jit_ptr,AMD64_R15,OFFSET(cpu_ppc_t,perf_counter));     jit_op_t *iop;
638      
639       iop = ppc32_op_emit_insn_output(cpu,1,"perf_cnt");
640       amd64_inc_membase_size(iop->ob_ptr,
641                              AMD64_R15,OFFSET(cpu_ppc_t,perf_counter),4);
642  }  }
643    
644  /* ======================================================================== */  /* ======================================================================== */
# Line 706  DECLARE_INSN(BCTR) Line 687  DECLARE_INSN(BCTR)
687    
688     /* set the return address */     /* set the return address */
689     if (insn & 1)     if (insn & 1)
690        ppc32_set_lr(iop,b->start_ia + (b->ppc_trans_pos << 2));        ppc32_set_lr(iop,b->start_ia + ((b->ppc_trans_pos+1) << 2));
691    
692     ppc32_jit_tcb_push_epilog(&iop->ob_ptr);     ppc32_jit_tcb_push_epilog(&iop->ob_ptr);
693     ppc32_op_emit_basic_opcode(cpu,JIT_OP_EOB);     ppc32_op_emit_basic_opcode(cpu,JIT_OP_EOB);
# Line 2588  DECLARE_INSN(MTCRF) Line 2569  DECLARE_INSN(MTCRF)
2569    
2570     ppc32_op_emit_load_gpr(cpu,hreg_rs,rs);     ppc32_op_emit_load_gpr(cpu,hreg_rs,rs);
2571    
2572     iop = ppc32_op_emit_insn_output(cpu,3,"mtcrf");     iop = ppc32_op_emit_insn_output(cpu,4,"mtcrf");
2573    
2574     for(i=0;i<8;i++)     for(i=0;i<8;i++)
2575        if (crm & (1 << (7 - i))) {        if (crm & (1 << (7 - i))) {
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