/[dynamips]/trunk/ppc32.h
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Contents of /trunk/ppc32.h

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Revision 12 - (show annotations)
Sat Oct 6 16:45:40 2007 UTC (11 years, 8 months ago) by dpavlin
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1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4 */
5
6 #ifndef __PPC_32_H__
7 #define __PPC_32_H__
8
9 #include <pthread.h>
10
11 #include "utils.h"
12 #include "rbtree.h"
13
14 /* CPU identifiers */
15 #define PPC32_PVR_405 0x40110000
16
17 /* Number of GPR (general purpose registers) */
18 #define PPC32_GPR_NR 32
19
20 /* Number of registers in FPU */
21 #define PPC32_FPU_REG_NR 32
22
23 /* Minimum page size: 4 Kb */
24 #define PPC32_MIN_PAGE_SHIFT 12
25 #define PPC32_MIN_PAGE_SIZE (1 << PPC32_MIN_PAGE_SHIFT)
26 #define PPC32_MIN_PAGE_IMASK (PPC32_MIN_PAGE_SIZE - 1)
27 #define PPC32_MIN_PAGE_MASK 0xFFFFF000
28
29 /* Number of instructions per page */
30 #define PPC32_INSN_PER_PAGE (PPC32_MIN_PAGE_SIZE/sizeof(ppc_insn_t))
31
32 /* Starting point for ROM */
33 #define PPC32_ROM_START 0xfff00100
34 #define PPC32_ROM_SP 0x00006000
35
36 /* Special Purpose Registers (SPR) */
37 #define PPC32_SPR_XER 1
38 #define PPC32_SPR_LR 8 /* Link Register */
39 #define PPC32_SPR_CTR 9 /* Count Register */
40 #define PPC32_SPR_DSISR 18
41 #define PPC32_SPR_DAR 19
42 #define PPC32_SPR_DEC 22 /* Decrementer */
43 #define PPC32_SPR_SDR1 25 /* Page Table Address */
44 #define PPC32_SPR_SRR0 26
45 #define PPC32_SPR_SRR1 27
46 #define PPC32_SPR_TBL_READ 268 /* Time Base Low (read) */
47 #define PPC32_SPR_TBU_READ 269 /* Time Base Up (read) */
48 #define PPC32_SPR_SPRG0 272
49 #define PPC32_SPR_SPRG1 273
50 #define PPC32_SPR_SPRG2 274
51 #define PPC32_SPR_SPRG3 275
52 #define PPC32_SPR_TBL_WRITE 284 /* Time Base Low (write) */
53 #define PPC32_SPR_TBU_WRITE 285 /* Time Base Up (write) */
54 #define PPC32_SPR_PVR 287 /* Processor Version Register */
55 #define PPC32_SPR_HID0 1008
56 #define PPC32_SPR_HID1 1009
57
58 #define PPC405_SPR_PID 945 /* Process Identifier */
59
60 /* Exception vectors */
61 #define PPC32_EXC_SYS_RST 0x00000100 /* System Reset */
62 #define PPC32_EXC_MC_CHK 0x00000200 /* Machine Check */
63 #define PPC32_EXC_DSI 0x00000300 /* Data memory access failure */
64 #define PPC32_EXC_ISI 0x00000400 /* Instruction fetch failure */
65 #define PPC32_EXC_EXT 0x00000500 /* External Interrupt */
66 #define PPC32_EXC_ALIGN 0x00000600 /* Alignment */
67 #define PPC32_EXC_PROG 0x00000700 /* FPU, Illegal instruction, ... */
68 #define PPC32_EXC_NO_FPU 0x00000800 /* FPU unavailable */
69 #define PPC32_EXC_DEC 0x00000900 /* Decrementer */
70 #define PPC32_EXC_SYSCALL 0x00000C00 /* System Call */
71 #define PPC32_EXC_TRACE 0x00000D00 /* Trace */
72 #define PPC32_EXC_FPU_HLP 0x00000E00 /* Floating-Point Assist */
73
74 /* Condition Register (CR) is accessed through 8 fields of 4 bits */
75 #define ppc32_get_cr_field(n) ((n) >> 2)
76 #define ppc32_get_cr_bit(n) (~(n) & 0x03)
77
78 /* Positions of LT, GT, EQ and SO bits in CR fields */
79 #define PPC32_CR_LT_BIT 3
80 #define PPC32_CR_GT_BIT 2
81 #define PPC32_CR_EQ_BIT 1
82 #define PPC32_CR_SO_BIT 0
83
84 /* CR0 (Condition Register Field 0) bits */
85 #define PPC32_CR0_LT_BIT 31
86 #define PPC32_CR0_LT (1 << PPC32_CR0_LT_BIT) /* Negative */
87 #define PPC32_CR0_GT_BIT 30
88 #define PPC32_CR0_GT (1 << PPC32_CR0_GT_BIT) /* Positive */
89 #define PPC32_CR0_EQ_BIT 29
90 #define PPC32_CR0_EQ (1 << PPC32_CR0_EQ_BIT) /* Zero */
91 #define PPC32_CR0_SO_BIT 28
92 #define PPC32_CR0_SO (1 << PPC32_CR0_SO_BIT) /* Summary overflow */
93
94 /* XER register */
95 #define PPC32_XER_SO_BIT 31
96 #define PPC32_XER_SO (1 << PPC32_XER_SO_BIT) /* Summary Overflow */
97 #define PPC32_XER_OV 0x40000000 /* Overflow */
98 #define PPC32_XER_CA_BIT 29
99 #define PPC32_XER_CA (1 << PPC32_XER_CA_BIT) /* Carry */
100 #define PPC32_XER_BC_MASK 0x0000007F /* Byte cnt (lswx/stswx) */
101
102 /* MSR (Machine State Register) */
103 #define PPC32_MSR_POW_MASK 0x00060000 /* Power Management */
104 #define PPC32_MSR_ILE 0x00010000 /* Exception Little-Endian Mode */
105 #define PPC32_MSR_EE 0x00008000 /* External Interrupt Enable */
106 #define PPC32_MSR_PR 0x00004000 /* Privilege Level (0=supervisor) */
107 #define PPC32_MSR_PR_SHIFT 14
108 #define PPC32_MSR_FP 0x00002000 /* Floating-Point Available */
109 #define PPC32_MSR_ME 0x00001000 /* Machine Check Enable */
110 #define PPC32_MSR_FE0 0x00000800 /* Floating-Point Exception Mode 0 */
111 #define PPC32_MSR_SE 0x00000400 /* Single-step trace enable */
112 #define PPC32_MSR_BE 0x00000200 /* Branch Trace Enable */
113 #define PPC32_MSR_FE1 0x00000100 /* Floating-Point Exception Mode 1 */
114 #define PPC32_MSR_IP 0x00000040 /* Exception Prefix */
115 #define PPC32_MSR_IR 0x00000020 /* Instruction address translation */
116 #define PPC32_MSR_DR 0x00000010 /* Data address translation */
117 #define PPC32_MSR_RI 0x00000002 /* Recoverable Exception */
118 #define PPC32_MSR_LE 0x00000001 /* Little-Endian mode enable */
119
120 #define PPC32_RFI_MSR_MASK 0x87c0ff73
121 #define PPC32_EXC_SRR1_MASK 0x0000ff73
122 #define PPC32_EXC_MSR_MASK 0x0006ef32
123
124 /* Number of BAT registers (8 for PowerPC 7448) */
125 #define PPC32_BAT_NR 8
126
127 /* Number of segment registers */
128 #define PPC32_SR_NR 16
129
130 /* Upper BAT register */
131 #define PPC32_UBAT_BEPI_MASK 0xFFFE0000 /* Block Effective Page Index */
132 #define PPC32_UBAT_BEPI_SHIFT 17
133 #define PPC32_UBAT_BL_MASK 0x00001FFC /* Block Length */
134 #define PPC32_UBAT_BL_SHIFT 2
135 #define PPC32_UBAT_XBL_MASK 0x0001FFFC /* Block Length */
136 #define PPC32_UBAT_XBL_SHIFT 2
137 #define PPC32_UBAT_VS 0x00000002 /* Supervisor mode valid bit */
138 #define PPC32_UBAT_VP 0x00000001 /* User mode valid bit */
139 #define PPC32_UBAT_PROT_MASK (PPC32_UBAT_VS|PPC32_UBAT_VP)
140
141 /* Lower BAT register */
142 #define PPC32_LBAT_BRPN_MASK 0xFFFE0000 /* Physical address */
143 #define PPC32_LBAT_BRPN_SHIFT 17
144 #define PPC32_LBAT_WIMG_MASK 0x00000078 /* Memory/cache access mode bits */
145 #define PPC32_LBAT_PP_MASK 0x00000003 /* Protection bits */
146
147 #define PPC32_BAT_ADDR_SHIFT 17
148
149 /* Segment Descriptor */
150 #define PPC32_SD_T 0x80000000
151 #define PPC32_SD_KS 0x40000000 /* Supervisor-state protection key */
152 #define PPC32_SD_KP 0x20000000 /* User-state protection key */
153 #define PPC32_SD_N 0x10000000 /* No-execute protection bit */
154 #define PPC32_SD_VSID_MASK 0x00FFFFFF /* Virtual Segment ID */
155
156 /* SDR1 Register */
157 #define PPC32_SDR1_HTABORG_MASK 0xFFFF0000 /* Physical base address */
158 #define PPC32_SDR1_HTABEXT_MASK 0x0000E000 /* Extended base address */
159 #define PPC32_SDR1_HTABMASK 0x000001FF /* Mask for page table address */
160 #define PPC32_SDR1_HTMEXT_MASK 0x00001FFF /* Extended mask */
161
162 /* Page Table Entry (PTE) size: 64-bits */
163 #define PPC32_PTE_SIZE 8
164
165 /* PTE entry (Up and Lo) */
166 #define PPC32_PTEU_V 0x80000000 /* Valid entry */
167 #define PPC32_PTEU_VSID_MASK 0x7FFFFF80 /* Virtual Segment ID */
168 #define PPC32_PTEU_VSID_SHIFT 7
169 #define PPC32_PTEU_H 0x00000040 /* Hash function */
170 #define PPC32_PTEU_API_MASK 0x0000003F /* Abbreviated Page index */
171 #define PPC32_PTEL_RPN_MASK 0xFFFFF000 /* Physical Page Number */
172 #define PPC32_PTEL_XPN_MASK 0x00000C00 /* Extended Page Number (0-2) */
173 #define PPC32_PTEL_XPN_SHIFT 9
174 #define PPC32_PTEL_R 0x00000100 /* Referenced bit */
175 #define PPC32_PTEL_C 0x00000080 /* Changed bit */
176 #define PPC32_PTEL_WIMG_MASK 0x00000078 /* Mem/cache access mode bits */
177 #define PPC32_PTEL_WIMG_SHIFT 3
178 #define PPC32_PTEL_X_MASK 0x00000004 /* Extended Page Number (3) */
179 #define PPC32_PTEL_X_SHIFT 2
180 #define PPC32_PTEL_PP_MASK 0x00000003 /* Page Protection bits */
181
182 /* DSISR register */
183 #define PPC32_DSISR_NOTRANS 0x40000000 /* No valid translation */
184 #define PPC32_DSISR_STORE 0x02000000 /* Store operation */
185
186 /* PowerPC 405 TLB definitions */
187 #define PPC405_TLBHI_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
188 #define PPC405_TLBHI_SIZE_MASK 0x00000380 /* Page Size */
189 #define PPC405_TLBHI_SIZE_SHIFT 7
190 #define PPC405_TLBHI_V 0x00000040 /* Valid TLB entry */
191 #define PPC405_TLBHI_E 0x00000020 /* Endianness */
192 #define PPC405_TLBHI_U0 0x00000010 /* User-Defined Attribute */
193
194 #define PPC405_TLBLO_RPN_MASK 0xFFFFFC00 /* Real Page Number */
195 #define PPC405_TLBLO_EX 0x00000200 /* Execute Enable */
196 #define PPC405_TLBLO_WR 0x00000100 /* Write Enable */
197 #define PPC405_TLBLO_ZSEL_MASK 0x000000F0 /* Zone Select */
198 #define PPC405_TLBLO_ZSEL_SHIFT 4
199 #define PPC405_TLBLO_W 0x00000008 /* Write-Through */
200 #define PPC405_TLBLO_I 0x00000004 /* Caching Inhibited */
201 #define PPC405_TLBLO_M 0x00000002 /* Memory Coherent */
202 #define PPC405_TLBLO_G 0x00000001 /* Guarded */
203
204 /* Number of TLB entries for PPC405 */
205 #define PPC405_TLB_ENTRIES 64
206
207 struct ppc405_tlb_entry {
208 m_uint32_t tlb_hi,tlb_lo,tid;
209 };
210
211 /* Memory operations */
212 enum {
213 PPC_MEMOP_LOOKUP = 0,
214
215 /* Instruction fetch operation */
216 PPC_MEMOP_IFETCH,
217
218 /* Load operations */
219 PPC_MEMOP_LBZ,
220 PPC_MEMOP_LHZ,
221 PPC_MEMOP_LWZ,
222
223 /* Load operation with sign-extend */
224 PPC_MEMOP_LHA,
225
226 /* Store operations */
227 PPC_MEMOP_STB,
228 PPC_MEMOP_STH,
229 PPC_MEMOP_STW,
230
231 /* Byte-Reversed operations */
232 PPC_MEMOP_LWBR,
233 PPC_MEMOP_STWBR,
234
235 /* String operations */
236 PPC_MEMOP_LSW,
237 PPC_MEMOP_STSW,
238
239 /* FPU operations */
240 PPC_MEMOP_LFD,
241 PPC_MEMOP_STFD,
242
243 /* ICBI - Instruction Cache Block Invalidate */
244 PPC_MEMOP_ICBI,
245
246 PPC_MEMOP_MAX,
247 };
248
249 /* PowerPC CPU type */
250 typedef struct cpu_ppc cpu_ppc_t;
251
252 /* Memory operation function prototype */
253 typedef fastcall void (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
254 u_int reg);
255
256 /* BAT type indexes */
257 enum {
258 PPC32_IBAT_IDX = 0,
259 PPC32_DBAT_IDX,
260 };
261
262 /* BAT register */
263 struct ppc32_bat_reg {
264 m_uint32_t reg[2];
265 };
266
267 /* BAT register programming */
268 struct ppc32_bat_prog {
269 int type,index;
270 m_uint32_t hi,lo;
271 };
272
273 /* MTS Instruction Cache and Data Cache */
274 #define PPC32_MTS_ICACHE PPC32_IBAT_IDX
275 #define PPC32_MTS_DCACHE PPC32_DBAT_IDX
276
277 /* FPU Coprocessor definition */
278 typedef struct {
279 m_uint64_t reg[PPC32_FPU_REG_NR];
280 }ppc_fpu_t;
281
282 /* Maximum number of breakpoints */
283 #define PPC32_MAX_BREAKPOINTS 8
284
285 /* zzz */
286 struct ppc32_vtlb_entry {
287 m_uint32_t vaddr;
288 m_uint32_t haddr;
289 };
290
291 /* PowerPC CPU definition */
292 struct cpu_ppc {
293 /* Instruction address */
294 m_uint32_t ia;
295
296 /* General Purpose registers */
297 m_uint32_t gpr[PPC32_GPR_NR];
298
299 struct ppc32_vtlb_entry vtlb[PPC32_GPR_NR];
300
301 /* Pending IRQ */
302 volatile m_uint32_t irq_pending,irq_check;
303
304 /* XER, Condition Register, Link Register, Count Register */
305 m_uint32_t xer,lr,ctr,reserve;
306 m_uint32_t xer_ca;
307
308 /* Condition Register (CR) fields */
309 u_int cr_fields[8];
310
311 /* MTS caches (Instruction+Data) */
312 mts32_entry_t *mts_cache[2];
313
314 /* Code page translation cache and physical page mapping */
315 ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map;
316
317 /* Virtual address to physical page translation */
318 fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
319 m_uint32_t *phys_page);
320
321 /* Memory access functions */
322 ppc_memop_fn mem_op_fn[PPC_MEMOP_MAX];
323
324 /* Memory lookup function (to load ELF image,...) */
325 void *(*mem_op_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid);
326
327 /* MTS slow lookup function */
328 mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
329 u_int cid,u_int op_code,u_int op_size,
330 u_int op_type,m_uint64_t *data,
331 mts32_entry_t *alt_entry);
332
333 /* IRQ counters */
334 m_uint64_t irq_count,timer_irq_count,irq_fp_count;
335 pthread_mutex_t irq_lock;
336
337 /* Current and free lists of translated code blocks */
338 ppc32_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list;
339
340 /* Executable page area */
341 void *exec_page_area;
342 size_t exec_page_area_size;
343 size_t exec_page_count,exec_page_alloc;
344 insn_exec_page_t *exec_page_free_list;
345 insn_exec_page_t *exec_page_array;
346
347 /* Idle PC value */
348 volatile m_uint32_t idle_pc;
349
350 /* Timer IRQs */
351 volatile u_int timer_irq_pending,timer_irq_armed;
352 u_int timer_irq_freq;
353 u_int timer_irq_check_itv;
354 u_int timer_drift;
355
356 /* IRQ disable flag */
357 volatile u_int irq_disable;
358
359 /* IBAT (Instruction) and DBAT (Data) registers */
360 struct ppc32_bat_reg bat[2][PPC32_BAT_NR];
361
362 /* Segment registers */
363 m_uint32_t sr[PPC32_SR_NR];
364
365 /* Page Table Address */
366 m_uint32_t sdr1;
367 void *sdr1_hptr;
368
369 /* MSR (Machine state register) */
370 m_uint32_t msr;
371
372 /* Interrupt Registers (SRR0/SRR1) */
373 m_uint32_t srr0,srr1,dsisr,dar;
374
375 /* SPRG registers */
376 m_uint32_t sprg[4];
377
378 /* PVR (Processor Version Register) */
379 m_uint32_t pvr;
380
381 /* Time-Base register */
382 m_uint64_t tb;
383
384 /* Decrementer */
385 m_uint32_t dec;
386
387 /* Hardware Implementation Dependent Registers */
388 m_uint32_t hid0,hid1;
389
390 /* String instruction position (lswi/stswi) */
391 u_int sw_pos;
392
393 /* PowerPC 405 TLB */
394 struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
395 m_uint32_t ppc405_pid;
396
397 /* MPC860 IMMR register */
398 m_uint32_t mpc860_immr;
399
400 /* FPU */
401 ppc_fpu_t fpu;
402
403 /* Generic CPU instance pointer */
404 cpu_gen_t *gen;
405
406 /* VM instance */
407 vm_instance_t *vm;
408
409 /* MTS cache statistics */
410 m_uint64_t mts_misses,mts_lookups;
411
412 /* JIT flush method */
413 u_int jit_flush_method;
414
415 /* Number of compiled pages */
416 u_int compiled_pages;
417
418 /* Fast memory operations use */
419 u_int fast_memop;
420
421 /* Direct block jump */
422 u_int exec_blk_direct_jump;
423
424 /* Current exec page (non-JIT) info */
425 m_uint64_t njm_exec_page;
426 mips_insn_t *njm_exec_ptr;
427
428 /* Performance counter (non-JIT) */
429 m_uint32_t perf_counter;
430
431 /* non-JIT mode instruction counter */
432 m_uint64_t insn_exec_count;
433
434 /* Breakpoints */
435 m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
436 u_int breakpoints_enabled;
437
438 /* JIT host register allocation */
439 char *jit_hreg_seq_name;
440 int ppc_reg_map[PPC32_GPR_NR];
441 struct hreg_map *hreg_map_list,*hreg_lru;
442 struct hreg_map hreg_map[JIT_HOST_NREG];
443 };
444
445 #define PPC32_CR_FIELD_OFFSET(f) \
446 (OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int)))
447
448 /* Get the full CR register */
449 static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu)
450 {
451 m_uint32_t cr = 0;
452 int i;
453
454 for(i=0;i<8;i++)
455 cr |= cpu->cr_fields[i] << (28 - (i << 2));
456
457 return(cr);
458 }
459
460 /* Set the CR fields given a CR value */
461 static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr)
462 {
463 int i;
464
465 for(i=0;i<8;i++)
466 cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F;
467 }
468
469 /* Get a CR bit */
470 static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit)
471 {
472 m_uint32_t res;
473
474 res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit);
475 return(res & 0x01);
476 }
477
478 /* Set a CR bit */
479 static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit)
480 {
481 cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit);
482 }
483
484 /* Clear a CR bit */
485 static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit)
486 {
487 cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit));
488 }
489
490 /* Reset a PowerPC CPU */
491 int ppc32_reset(cpu_ppc_t *cpu);
492
493 /* Initialize a PowerPC processor */
494 int ppc32_init(cpu_ppc_t *cpu);
495
496 /* Delete a PowerPC processor */
497 void ppc32_delete(cpu_ppc_t *cpu);
498
499 /* Set the processor version register (PVR) */
500 void ppc32_set_pvr(cpu_ppc_t *cpu,m_uint32_t pvr);
501
502 /* Set idle PC value */
503 void ppc32_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr);
504
505 /* Timer IRQ */
506 void *ppc32_timer_irq_run(cpu_ppc_t *cpu);
507
508 /* Determine an "idling" PC */
509 int ppc32_get_idling_pc(cpu_gen_t *cpu);
510
511 /* Generate an exception */
512 void ppc32_trigger_exception(cpu_ppc_t *cpu,u_int exc_vector);
513
514 /* Trigger the decrementer exception */
515 void ppc32_trigger_timer_irq(cpu_ppc_t *cpu);
516
517 /* Trigger IRQs */
518 fastcall void ppc32_trigger_irq(cpu_ppc_t *cpu);
519
520 /* Virtual breakpoint */
521 fastcall void ppc32_run_breakpoint(cpu_ppc_t *cpu);
522
523 /* Add a virtual breakpoint */
524 int ppc32_add_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);
525
526 /* Remove a virtual breakpoint */
527 void ppc32_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);
528
529 /* Set a register */
530 void ppc32_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val);
531
532 /* Dump registers of a PowerPC processor */
533 void ppc32_dump_regs(cpu_gen_t *cpu);
534
535 /* Dump MMU registers */
536 void ppc32_dump_mmu(cpu_gen_t *cpu);
537
538 /* Load a raw image into the simulated memory */
539 int ppc32_load_raw_image(cpu_ppc_t *cpu,char *filename,m_uint32_t vaddr);
540
541 /* Load an ELF image into the simulated memory */
542 int ppc32_load_elf_image(cpu_ppc_t *cpu,char *filename,int skip_load,
543 m_uint32_t *entry_point);
544
545 /* Run PowerPC code in step-by-step mode */
546 void *ppc32_exec_run_cpu(cpu_gen_t *gen);
547
548 #endif

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