--- upstream/dynamips-0.2.7-RC2/ppc32.h	2007/10/06 16:24:54	8
+++ trunk/ppc32.h	2007/10/06 16:45:40	12
@@ -26,6 +26,9 @@
 #define PPC32_MIN_PAGE_IMASK   (PPC32_MIN_PAGE_SIZE - 1)
 #define PPC32_MIN_PAGE_MASK    0xFFFFF000
 
+/* Number of instructions per page */
+#define PPC32_INSN_PER_PAGE    (PPC32_MIN_PAGE_SIZE/sizeof(ppc_insn_t))
+
 /* Starting point for ROM */
 #define PPC32_ROM_START  0xfff00100
 #define PPC32_ROM_SP     0x00006000
@@ -247,8 +250,8 @@
 typedef struct cpu_ppc cpu_ppc_t;
 
 /* Memory operation function prototype */
-typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
-                                       u_int reg);
+typedef fastcall void (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
+                                      u_int reg);
 
 /* BAT type indexes */
 enum {
@@ -279,6 +282,12 @@
 /* Maximum number of breakpoints */
 #define PPC32_MAX_BREAKPOINTS  8
 
+/* zzz */
+struct ppc32_vtlb_entry {
+   m_uint32_t vaddr;
+   m_uint32_t haddr;
+};
+
 /* PowerPC CPU definition */
 struct cpu_ppc {
    /* Instruction address */
@@ -287,6 +296,8 @@
    /* General Purpose registers */
    m_uint32_t gpr[PPC32_GPR_NR];
 
+   struct ppc32_vtlb_entry vtlb[PPC32_GPR_NR];
+
    /* Pending IRQ */
    volatile m_uint32_t irq_pending,irq_check;
 
@@ -317,7 +328,7 @@
    mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
                                      u_int cid,u_int op_code,u_int op_size,
                                      u_int op_type,m_uint64_t *data,
-                                     u_int *exc,mts32_entry_t *alt_entry);
+                                     mts32_entry_t *alt_entry);
 
    /* IRQ counters */
    m_uint64_t irq_count,timer_irq_count,irq_fp_count;
@@ -383,6 +394,9 @@
    struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
    m_uint32_t ppc405_pid;
 
+   /* MPC860 IMMR register */
+   m_uint32_t mpc860_immr;
+
    /* FPU */
    ppc_fpu_t fpu;
 
@@ -412,7 +426,7 @@
    mips_insn_t *njm_exec_ptr;
 
    /* Performance counter (non-JIT) */
-   m_uint64_t perf_counter;
+   m_uint32_t perf_counter;
 
    /* non-JIT mode instruction counter */
    m_uint64_t insn_exec_count;
@@ -420,6 +434,12 @@
    /* Breakpoints */
    m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
    u_int breakpoints_enabled;
+
+   /* JIT host register allocation */
+   char *jit_hreg_seq_name;
+   int ppc_reg_map[PPC32_GPR_NR];
+   struct hreg_map *hreg_map_list,*hreg_lru;
+   struct hreg_map hreg_map[JIT_HOST_NREG];
 };
 
 #define PPC32_CR_FIELD_OFFSET(f) \