/[dynamips]/trunk/ppc32.h
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Diff of /trunk/ppc32.h

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upstream/dynamips-0.2.7-RC1/ppc32.h revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC trunk/ppc32.h revision 12 by dpavlin, Sat Oct 6 16:45:40 2007 UTC
# Line 26  Line 26 
26  #define PPC32_MIN_PAGE_IMASK   (PPC32_MIN_PAGE_SIZE - 1)  #define PPC32_MIN_PAGE_IMASK   (PPC32_MIN_PAGE_SIZE - 1)
27  #define PPC32_MIN_PAGE_MASK    0xFFFFF000  #define PPC32_MIN_PAGE_MASK    0xFFFFF000
28    
29    /* Number of instructions per page */
30    #define PPC32_INSN_PER_PAGE    (PPC32_MIN_PAGE_SIZE/sizeof(ppc_insn_t))
31    
32  /* Starting point for ROM */  /* Starting point for ROM */
33  #define PPC32_ROM_START  0xfff00100  #define PPC32_ROM_START  0xfff00100
34  #define PPC32_ROM_SP     0x00006000  #define PPC32_ROM_SP     0x00006000
# Line 68  Line 71 
71  #define PPC32_EXC_TRACE     0x00000D00   /* Trace */  #define PPC32_EXC_TRACE     0x00000D00   /* Trace */
72  #define PPC32_EXC_FPU_HLP   0x00000E00   /* Floating-Point Assist */  #define PPC32_EXC_FPU_HLP   0x00000E00   /* Floating-Point Assist */
73    
74    /* Condition Register (CR) is accessed through 8 fields of 4 bits */
75    #define ppc32_get_cr_field(n)  ((n) >> 2)
76    #define ppc32_get_cr_bit(n)    (~(n) & 0x03)
77    
78    /* Positions of LT, GT, EQ and SO bits in CR fields */
79    #define PPC32_CR_LT_BIT  3
80    #define PPC32_CR_GT_BIT  2
81    #define PPC32_CR_EQ_BIT  1
82    #define PPC32_CR_SO_BIT  0
83    
84  /* CR0 (Condition Register Field 0) bits */  /* CR0 (Condition Register Field 0) bits */
85  #define PPC32_CR0_LT_BIT    31  #define PPC32_CR0_LT_BIT    31
86  #define PPC32_CR0_LT        (1 << PPC32_CR0_LT_BIT)   /* Negative */  #define PPC32_CR0_LT        (1 << PPC32_CR0_LT_BIT)   /* Negative */
# Line 237  enum { Line 250  enum {
250  typedef struct cpu_ppc cpu_ppc_t;  typedef struct cpu_ppc cpu_ppc_t;
251    
252  /* Memory operation function prototype */  /* Memory operation function prototype */
253  typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,  typedef fastcall void (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
254                                         u_int reg);                                        u_int reg);
255    
256  /* BAT type indexes */  /* BAT type indexes */
257  enum {  enum {
# Line 269  typedef struct { Line 282  typedef struct {
282  /* Maximum number of breakpoints */  /* Maximum number of breakpoints */
283  #define PPC32_MAX_BREAKPOINTS  8  #define PPC32_MAX_BREAKPOINTS  8
284    
285    /* zzz */
286    struct ppc32_vtlb_entry {
287       m_uint32_t vaddr;
288       m_uint32_t haddr;
289    };
290    
291  /* PowerPC CPU definition */  /* PowerPC CPU definition */
292  struct cpu_ppc {  struct cpu_ppc {
293     /* Instruction address */     /* Instruction address */
# Line 277  struct cpu_ppc { Line 296  struct cpu_ppc {
296     /* General Purpose registers */     /* General Purpose registers */
297     m_uint32_t gpr[PPC32_GPR_NR];     m_uint32_t gpr[PPC32_GPR_NR];
298    
299       struct ppc32_vtlb_entry vtlb[PPC32_GPR_NR];
300    
301     /* Pending IRQ */     /* Pending IRQ */
302     volatile m_uint32_t irq_pending,irq_check;     volatile m_uint32_t irq_pending,irq_check;
303    
304     /* XER, Condition Register, Link Register, Count Register */     /* XER, Condition Register, Link Register, Count Register */
305     m_uint32_t xer,cr,lr,ctr,reserve;     m_uint32_t xer,lr,ctr,reserve;
306     m_uint32_t xer_ca;     m_uint32_t xer_ca;
307    
308       /* Condition Register (CR) fields */
309       u_int cr_fields[8];
310    
311     /* MTS caches (Instruction+Data) */     /* MTS caches (Instruction+Data) */
312     mts32_entry_t *mts_cache[2];     mts32_entry_t *mts_cache[2];
313    
314     /* Code page translation cache */     /* Code page translation cache and physical page mapping */
315     ppc32_jit_tcb_t **exec_phys_map;     ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map;
316    
317     /* Virtual address to physical page translation */     /* Virtual address to physical page translation */
318     fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,     fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
# Line 304  struct cpu_ppc { Line 328  struct cpu_ppc {
328     mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,     mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
329                                       u_int cid,u_int op_code,u_int op_size,                                       u_int cid,u_int op_code,u_int op_size,
330                                       u_int op_type,m_uint64_t *data,                                       u_int op_type,m_uint64_t *data,
331                                       u_int *exc,mts32_entry_t *alt_entry);                                       mts32_entry_t *alt_entry);
332    
333     /* IRQ counters */     /* IRQ counters */
334     m_uint64_t irq_count,timer_irq_count,irq_fp_count;     m_uint64_t irq_count,timer_irq_count,irq_fp_count;
# Line 370  struct cpu_ppc { Line 394  struct cpu_ppc {
394     struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];     struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
395     m_uint32_t ppc405_pid;     m_uint32_t ppc405_pid;
396    
397       /* MPC860 IMMR register */
398       m_uint32_t mpc860_immr;
399    
400     /* FPU */     /* FPU */
401     ppc_fpu_t fpu;     ppc_fpu_t fpu;
402    
# Line 391  struct cpu_ppc { Line 418  struct cpu_ppc {
418     /* Fast memory operations use */     /* Fast memory operations use */
419     u_int fast_memop;     u_int fast_memop;
420    
421     /* IRQ idling preemption */     /* Direct block jump */
422     u_int irq_idle_preempt[32];     u_int exec_blk_direct_jump;
423    
424     /* Current exec page (non-JIT) info */     /* Current exec page (non-JIT) info */
425     m_uint64_t njm_exec_page;     m_uint64_t njm_exec_page;
426     mips_insn_t *njm_exec_ptr;     mips_insn_t *njm_exec_ptr;
427    
428     /* Performance counter (non-JIT) */     /* Performance counter (non-JIT) */
429     m_uint64_t perf_counter;     m_uint32_t perf_counter;
430    
431     /* non-JIT mode instruction counter */     /* non-JIT mode instruction counter */
432     m_uint64_t insn_exec_count;     m_uint64_t insn_exec_count;
# Line 407  struct cpu_ppc { Line 434  struct cpu_ppc {
434     /* Breakpoints */     /* Breakpoints */
435     m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];     m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
436     u_int breakpoints_enabled;     u_int breakpoints_enabled;
437    
438       /* JIT host register allocation */
439       char *jit_hreg_seq_name;
440       int ppc_reg_map[PPC32_GPR_NR];
441       struct hreg_map *hreg_map_list,*hreg_lru;
442       struct hreg_map hreg_map[JIT_HOST_NREG];
443  };  };
444    
445    #define PPC32_CR_FIELD_OFFSET(f) \
446       (OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int)))
447    
448    /* Get the full CR register */
449    static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu)
450    {
451       m_uint32_t cr = 0;
452       int i;
453    
454       for(i=0;i<8;i++)
455          cr |= cpu->cr_fields[i] << (28 - (i << 2));
456    
457       return(cr);
458    }
459    
460    /* Set the CR fields given a CR value */
461    static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr)
462    {
463       int i;
464    
465       for(i=0;i<8;i++)
466          cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F;
467    }
468    
469    /* Get a CR bit */
470    static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit)
471    {
472       m_uint32_t res;
473    
474       res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit);
475       return(res & 0x01);
476    }
477    
478    /* Set a CR bit */
479    static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit)
480    {
481       cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit);
482    }
483    
484    /* Clear a CR bit */
485    static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit)
486    {
487       cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit));
488    }
489    
490  /* Reset a PowerPC CPU */  /* Reset a PowerPC CPU */
491  int ppc32_reset(cpu_ppc_t *cpu);  int ppc32_reset(cpu_ppc_t *cpu);
492    
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